Clock recovery system in digital rotary scan magnetic playback devices

Claim 2

A clock recovery system in a digital magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a phase locked loop having a controlled signal generator means for providing a playback clock signal, a phase detector means having a first input coupled to receive said playback clock signal and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means having an output coupled to provide said phase error signal; a delay means coupled to receive said phase error signal and to repeatedly delay said received signal by one recurrent interval of said periodic signal component; and means coupled to sum said phase error signal and said repeatedly delayed signal and to apply said summed signals to a control input of said controlled signal generator means.

Claim 3

The system of claim 1 further comprising a first attenuation means coupled between an output and an input of said delay means and wherein said means for summing has a first input coupled to an output of said phase detector means, a second input coupled to receive an output signal of said first attenuation means and an output coupled to both said input of said delay means and said control input of said controlled signal generator means.

Claim 4

The system of claim 1 further comprising a first attenuation means coupled between an output and an input of said delay means and wherein said means for summing comprises a first summing means having a first input coupled to an output of said phase detector means, a second input coupled to receive an output signal of said delay means and an output coupled to said control input of said controlled signal generator means, and a second summing means having a first input coupled to receive said phase error signal provided by said phase detector means, a second input coupled to receive an output signal of said first attenuation means and an output coupled to an input of said delay means.

Claim 5

The system of claim 3 further comprising a second attenuation means coupled between said output of said delay means and said first summing means.

Claim 6

The system of claim 4 further comprising a first and a second switch means, said first switch means being coupled between said output of said phase detector means and said first and second summing means, and said second switch means being coupled in parallel with said first attenuation means, said first and second switch means having respective control inputs coupled to receive a dropout control signal for opening said first switch means and closing said second switch means in response to a dropout in said playback signal.

Claim 7

The system of claim 1 further comprising a loop filter means coupled between said output of said phase detector means and said first and second summing means.

Claim 8

The system of claim 6 wherein said loop filter means comprises a low pass filter and integrator means.

Claim 9

The system of claim 1 wherein said delay means comprises a plurality of delay circuits coupled in series, each delay circuit providing a signal delay by one said recurrent interval of said periodic error signal component, wherein said means for summing is coupled to receive and sum an output signal of said phase detector means and said respective delay circuits and to apply said summed signals to said control input of said controlled signal generator means.

Claim 10

The system of claim 1 wherein said delay means comprises a plurality of delay circuits coupled in series, each delay circuit providing a signal delay by one said recurrent interval of said periodic error signal component, wherein said means for summing comprises a first summing means coupled to receive and sum an output signal of said respective delay circuits and a second summing means coupled to receive an output signal of said first summing means and an output signal of said phase detector means and to apply said summed signals to said control input of said controlled signal generator means.

Claim 11

The system of claim 9 further comprising an attenuation means coupled between said first and said second summing means.

Claim 12

The system of claim 10 further comprising a first switch means coupled between an output of said phase detector means and an input of a first one of said plurality of delay circuits, and a series combination of a second switch means with a divider means coupled between said input of said first delay means and said output of said first summing means, said divider means being coupled to divide an output signal of said first summing means by an integral number equal to a number of said plurality of delay circuits, said first and second switch means having a control input coupled to receive a dropout control signal for opening said first switch means and closing said second switch means in response to a dropout in said playback signal.

Claim 13

A clock recovery system in a digital rotary scan magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a delay means coupled to receive said phase error signal and to repeatedly delay said received signal by one recurrent interval of said periodic signal component; an attenuation means coupled between an output and an input of said delay means; and means for summing said attenuated delayed signal and said phase error signal and to apply said summed signals to said control input of said signal generator means.

Claim 14

A clock recovery system in a digital rotary scan magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a delay means coupled to receive said phase error signal and to repeatedly delay said received signal by one recurrent interval of said periodic signal component; an attenuation means coupled between an output and an input of said delay means; and means for summing said attenuated delayed signal and said phase error signal and to apply said summed signals to said control input of said signal generator means.

Claim 15

A clock recovery system in a digital rotary scan magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a loop filter means coupled to receive and filter said phase error signal; a delay means coupled to receive an output signal of said loop filter means and to delay said received signal by one recurrent interval of said periodic signal component; an attenuation means coupled between an output and an input of said delay means; a first summing means having a first input coupled to an output of said loop filter means, a second input coupled to receive an output signal of said first attenuation means and an output coupled to said input of said delay means; a second summing means coupled to receive said output signal of said delay means and said output signal of the loop filter means and to apply said summed signals to said control input of said signal generator means; and a second attenuation means coupled between said output of said delay means and said second summing means.

Claim 16

A clock recovery system in a digital rotary scan magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a loop filter means coupled to receive and filter said phase error signal; a delay means coupled to receive an output signal of said loop filter means and to delay said received signal by one recurrent interval of said periodic signal component; an attenuation means coupled between an output and an input of said delay means; a first summing means having a first input coupled to an output of said loop filter means, a second input coupled to receive an output signal of said first attenuation means and an output coupled to said input of said delay means; a second summing means coupled to receive said output signal of said delay means and said output signal of the loop filter means and to apply said summed signals to said control input of said signal generator means; and a second attenuation means coupled between said output of said delay means and said second summing means.

Claim 17

The system of claim 13 further comprising a first and a second switch means, said first switch means being coupled between an output of said loop filter means and said first and second summing means, and said second switch means being coupled in parallel with said first attenuation means, said first and second switch means having respective control inputs coupled to receive a dropout control signal for opening said first switch means and closing said second switch means in response to a dropout in said playback signal.

Claim 18

A clock recovery system in a digital magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a loop filter means coupled to receive and filter said phase error signal; a plurality of delay circuits coupled in series, each providing a signal delay by one recurrent interval of said periodic signal component, a first one of said delay circuits coupled to receive an output signal of said loop filter means; and a first summing means coupled to receive and sum an output signal of said respective delay circuits and said output signal of said loop filter means and to apply said summed signals to said control input of said playback clock signal generator means.

Claim 19

A clock recovery system in a digital magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a loop filter means coupled to receive and filter said phase error signal; a plurality of delay circuits coupled in series, each providing a signal delay by one recurrent interval of said periodic signal component, a first one of said delay circuits coupled to receive an output signal of said loop filter means; and a first summing means coupled to receive and sum an output signal of said respective delay circuits and said output signal of said loop filter means and to apply said summed signals to said control input of said playback clock signal generator means.

Claim 20

A clock recovery system in a digital rotary scan magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a loop filter means coupled to receive and filter said phase error signal; a plurality of delay circuits coupled in series, each providing a signal delay by one recurrent interval of said periodic signal component, a first one of said delay circuits coupled to receive an output signal of said loop filter means; a first summing means coupled to receive and sum an output signal of said respective delay circuits; a second summing means coupled to receive said output signal of said first summing means and an output signal of said loop filter means and to apply said summed signals to said control input of said playback clock signal generator means; and a second attenuation means coupled between said first and said second summing means.

Claim 21

A clock recovery system in a digital rotary scan magnetic playback device wherein a phase error signal is provided which has a periodic signal component due to time base variations of a playback signal and a random signal component due to noise, comprising: a controlled playback clock signal generator means; a phase detector means having a first input coupled to receive a playback clock signal from said signal generator means and a second input coupled to receive an input signal indicating logic level transitions of said playback signal, said phase detector means coupled to provide said phase error signal; a loop filter means coupled to receive and filter said phase error signal; a plurality of delay circuits coupled in series, each providing a signal delay by one recurrent interval of said periodic signal component, a first one of said delay circuits coupled to receive an output signal of said loop filter means; a first summing means coupled to receive and sum an output signal of said respective delay circuits; a second summing means coupled to receive said output signal of said first summing means and an output signal of said loop filter means and to apply said summed signals to said control input of said playback clock signal generator means; and a second attenuation means coupled between said first and said second summing means.

Claim 22

The system of claim 16 further comprising a first switch means coupled between an output of said loop filter means and an input of a first one of said plurality of delay circuits, and a series combination of a second switch means with a divider means coupled between said input of said first delay means and an output of said first summing means, said divider means being coupled to divide an output signal of said first summing means by an integral number equal to a number of said plurality of delay circuits, said first and second switch means having respective control inputs coupled to receive a dropout control signal for opening said first switch means and closing said second switch means in response to a dropout in said playback signal.