US4528512A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Timing synchronizing circuit for demodulators
Assignee: NEC Corp
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Filing: 1984-03-02
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Granted: 1985-07-09
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Expires: 2004-03-02
Abstract
Abstract In a timing synchronizing circuit wherein a timing signal is regenerated from a baseband signal subjected to a bandwidth limitation, there are provided a voltage controlled oscillator whose oscillation frequency varies in accordance with a control signal, an A/D converter which samples and shapes the baseband signal by utilizing the output of the voltage controlled oscillator, a decision circuit for deciding the polarity of a differential coefficient of the baseband signal at an optimum sampling point on the basis of an output of the A/D converter, and a logic circuit responsive to the output of the decision circuit to apply a logical operation to a decision signal derived from the A/D converter and which decides whether or not the baseband signal shifts from a level corresponding to the optimum sampling point, thereby producing the control signal for the voltage controlled oscillator. According to this circuit the regenerated timing signal contains only a negligible amount of jitter components and always maintains an optimum timing without using any phase adjustment.
Inventors
- 👤 Yasuharu Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 22:47
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0334; H04L7/0335
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
120 words
A timing synchronizing circuit for regenerating a timing signal from a baseband signal subjected to a bandwidth limitation, comprising: voltage controlled oscillator means responsive to a control signal for providing said timing signal; A/D converter means responsive to said timing signal for sampling said baseband signal and converting it into a plurality of digital signals; decision circuit means responsive to an output of said A/D converter means for deciding the polarity of a differential coefficient of said baseband signal at an optimum sampling point; and logic circuit means responsive to the output of said decision circuit means for deciding whether or not said baseband signal shifts from a level corresponding to said optimum sampling point, thereby providing said control signal.
Claim 2
Dependent Claim
120 words
A timing synchronizing circuit for regenerating a timing signal from a baseband signal subjected to a bandwidth limitation, comprising: voltage controlled oscillator means responsive to a control signal for providing said timing signal; A/D converter means responsive to said timing signal for sampling said baseband signal and converting it into a plurality of digital signals; decision circuit means responsive to an output of said A/D converter means for deciding the polarity of a differential coefficient of said baseband signal at an optimum sampling point; and logic circuit means responsive to the output of said decision circuit means for deciding whether or not said baseband signal shifts from a level corresponding to said optimum sampling point, thereby providing said control signal.
Claim 3
Dependent Claim
23 words
A timing synchronizing circuit according to claim 1 wherein said control signal is applied to said voltage controlled oscillator via a low-pass filter.
Claim 4
Dependent Claim
214 words
A demodulation apparatus comprising in combination a demodulation circuit for demodulating a carrier wave modulated with a baseband signal subjected to a bandwidth limitation and a timing synchronizing circuit for regenerating a timing signal from the demodulated baseband signal; said timing synchronizing circuit including a plurality of A/D converter means responsive to said timing signal for sampling said demodulated baseband signal and providing a plurality of digital signals; and at least one clock synchronizing circuit including a voltage controlled oscillator responsive to a control signal for providing said timing signal, a decision circuit reponsive to said timing signal and an output of said A/D converter means for deciding the polarity of a differential coefficient of said baseband signal at an optimum sampling point, and a logic circuit responsive to said timing signal, the output of said decision circuit and the output of said A/D converter means, for deciding whether or not said baseband signal shifts from a level corresponding to said optimum sampling point, thereby providing said control signal; said demodulation circuit including a carrier synchronizing circuit responsive to the outputs of said timing synchronizing circuit for providing a reference carrier wave, a pair of phase detectors for detecting the modulated carrier wave with said reference carrier wave and providing said demodulated baseband signal.
Claim 5
Dependent Claim
214 words
A demodulation apparatus comprising in combination a demodulation circuit for demodulating a carrier wave modulated with a baseband signal subjected to a bandwidth limitation and a timing synchronizing circuit for regenerating a timing signal from the demodulated baseband signal; said timing synchronizing circuit including a plurality of A/D converter means responsive to said timing signal for sampling said demodulated baseband signal and providing a plurality of digital signals; and at least one clock synchronizing circuit including a voltage controlled oscillator responsive to a control signal for providing said timing signal, a decision circuit reponsive to said timing signal and an output of said A/D converter means for deciding the polarity of a differential coefficient of said baseband signal at an optimum sampling point, and a logic circuit responsive to said timing signal, the output of said decision circuit and the output of said A/D converter means, for deciding whether or not said baseband signal shifts from a level corresponding to said optimum sampling point, thereby providing said control signal; said demodulation circuit including a carrier synchronizing circuit responsive to the outputs of said timing synchronizing circuit for providing a reference carrier wave, a pair of phase detectors for detecting the modulated carrier wave with said reference carrier wave and providing said demodulated baseband signal.
Claim 6
Dependent Claim
22 words
A demodulation apparatus according to claim 3 comprising a plurality of clock synchronizing circuits respectively associated with the plurality of A/D converters.
Claim 7
Dependent Claim
24 words
A demodulation apparatus according to claim 3 wherein said A/D converters are responsive to the timing signal produced from a single clock synchronizing circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-07-08 | 1989-01-07 | 1989-07-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-07-08 | 1993-01-07 | 1993-07-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-07-08 | 1997-01-07 | 1997-07-09 | $7700.00 | Window Closed / Lapsed |