US4963508A
Expired / Lapsed
US
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Method of making an epitaxial gallium arsenide semiconductor wafer using a strained layer superlattice
Assignee: Daido Steel Co Ltd
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Filing: 1990-02-22
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Granted: 1990-10-16
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Expires: 2010-02-22
Abstract
Abstract A semiconductor wafer having an epitaxial GaAs layer, including a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100); and at least one intermediate layer epitaxially grown on the major surface of the monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between the Si substrate and the epitaxial GaAs layer which is epitaxially grown on a major surface of the top layer of the at least one intermediate layer. The at least one intermediate layer may comprise one or mor GaP/GaAsP, GaAsP/GaAs superlattice layers. the wafer may be used to produce a seimconductor light emitting element which has a plurality of crystalline gaAs layers including a light emitting layer epitaxially grown on the GaAs layer on the intermediate layer. The wafer may also be used to produce a compound semiconductor device such as amplifying and switching elements, light emitting and receiving elements and photovolataic elements. Methods for producing the semiconductor wafer, light emitting element and compound semiconductor devices are also disclosed.
Inventors
- 👤 Masayoshi Umeno
- 👤 Shiro Sakai
- 👤 Shinichiro Yahagi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:38
CPC Classifications
H; H10; H10F; H10F10/00; H10F10/10; H10F10/14; H10F10/144; H10D; H10D62/00; H10D62/40; H10D62/405; H10D62/80; H10D62/82; H10F30/00; H10F30/20; H10F30/21; H10F30/22; H10F30/223; H10F71/00; H10F71/127; H10H; H10H20/00; H10H20/01; H10H20/011; H10H20/013; H10H20/0133; H10P; H10P14/00; H10P14/20; H10P14/24; H10P14/29; H10P14/2901; H10P14/2902; H10P14/2905; H10P14/2926; H10P14/32; H10P14/3202; H10P14/3214; H10P14/3218; H10P14/3221; H10P14/3242; H10P14/3244; H10P14/3251; H10P14/3252; H10P14/34; H10P14/3402; H10P14/3414; H10P14/3421; H10P14/3438; H10P14/3441; Y; Y02; Y02E; Y02E10/00; Y02E10/50; Y02E10/544; Y10; Y10S; Y10S117/00; Y10S117/901; Y10S117/902; Y10S148/00; Y10S148/072; Y10S148/097; Y10S148/16; Y10S438/00; Y10S438/933; Y10S438/938
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
161 words
A method of producing a semiconductor wafer having an epitaxial GaAs layer, comprising the steps of: preparting a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100); forming at least one intermediate layer by epitaxy on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said GaAs layer; said at least one intermediate layer consisting essentially of GaP layer formed on said Si substrate, a GaP/GaAsP superlattice formed on said GAP layer, and a GaAsP/GaAs superlattice on said GaP/GaAsP superlattice, wherein said GaP layer has a greater thickness than the total thickness of said superlattices; and said GaP/GaAsP superlattice and said GaAsP/GaAs superlattice having an average lattice constant between the lattice constant of said Si substrate and the lattice constant of said GaAs layer; and forming said epitaxial GaAs layer on said said GaP/GaAsP superlattice.
Claim 2
Independent Claim
161 words
A method of producing a semiconductor wafer having an epitaxial GaAs layer, comprising the steps of: preparting a monocrystalline Si substrate having a major surface which is inclined at an off angle between 0.5° and 5° with respect to (100); forming at least one intermediate layer by epitaxy on said major surface of said monocrystalline Si substrate, as a buffer layer for accommodating a lattice mismatch between said Si substrate and said GaAs layer; said at least one intermediate layer consisting essentially of GaP layer formed on said Si substrate, a GaP/GaAsP superlattice formed on said GAP layer, and a GaAsP/GaAs superlattice on said GaP/GaAsP superlattice, wherein said GaP layer has a greater thickness than the total thickness of said superlattices; and said GaP/GaAsP superlattice and said GaAsP/GaAs superlattice having an average lattice constant between the lattice constant of said Si substrate and the lattice constant of said GaAs layer; and forming said epitaxial GaAs layer on said said GaP/GaAsP superlattice.
Claim 3
Independent Claim
120 words
A method of producing a semiconductor wafer, comprising the steps of: preparing a monocrystalline Si substrate; forming a GaP layer by epitaxy on a major surface of said monocrystalline Si substrate; forming at least one GaP/GaAsP superlattice layer by epitaxy on said GaP layer; forming at least one GaAsP/GaAs superlattice layer by epitaxy on said at least one GaP/GaAsP superlattice layer; and forming a GaAs layer by epitaxy on said at least one GaAsP/GaAs superlattice layer, wherein said GaP layer has a greater thickness than the total thickness of said superlattices; and said GaP/GaAsP superlattice and said GaAsP/GaAs superlattice having an average lattice constant between the lattice constant of said Si substrate and the lattice constant of said GaAs layer.
Claim 4
Independent Claim
120 words
A method of producing a semiconductor wafer, comprising the steps of: preparing a monocrystalline Si substrate; forming a GaP layer by epitaxy on a major surface of said monocrystalline Si substrate; forming at least one GaP/GaAsP superlattice layer by epitaxy on said GaP layer; forming at least one GaAsP/GaAs superlattice layer by epitaxy on said at least one GaP/GaAsP superlattice layer; and forming a GaAs layer by epitaxy on said at least one GaAsP/GaAs superlattice layer, wherein said GaP layer has a greater thickness than the total thickness of said superlattices; and said GaP/GaAsP superlattice and said GaAsP/GaAs superlattice having an average lattice constant between the lattice constant of said Si substrate and the lattice constant of said GaAs layer.
Claim 5
Dependent Claim
43 words
A method according to claim 3, further comprising annealing said monocrystalline Si substrate by subjecting the Si substrate at a temperature between 600° C. and 1100° C., to a flow of PH 3 gas for a period ranging from 1 to 60 minutes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |