Patent US4959703A successfully refreshed from Google Patents.
US4959703A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Turn-on/off driving technique for insulated gate thyristor
Assignee: Toshiba Corp
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Filing: 1989-06-28
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Granted: 1990-09-25
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Expires: 2009-06-28
Abstract
Abstract A turn-on/off driving technique for an insulated gate thyristor which has a first gate electrode insulatively provided above a first base layer and fuctioning as a gate of MOSFET, and a second gate electrode formed on the second base layer. To drive the turn-on of the thyristor, a first voltage for rendering the MOSFET conductive is applied to the first gate electrode, while substantially simultaneously a second voltage for producing forward biasing between the second base layer and a second emitter layer is applied to the second gate electrode. To turn-off drive the thyristor, a third voltage for reverse biasing between the second emitter layer and the second base layer to stop the operation of the thyristor is applied to the second gate, while the MOSFET is kept conductive. The thyristor starts turning off in response to the voltage application. At this time, charge carriers exhausted from the second emitter layer are allowed to flow into the first base layer through the channel region of the MOSFET, thereby suppressing the local concentration of the turn-off current in the thyristor.
Inventors
- 👤 Tsuneo Ogura
- 👤 Akio Nakagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:34
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/192; H10D62/206; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/72; H03K17/73; H03K17/732; H10D18/00; H10D18/40; H10D18/60; H10D62/13; H10D62/141; H10D62/142
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
168 words
An insulated gate thyristor comprising: a first emitter layer; a first base layer; a second emitter layer; a second base layer having a bottom section; a first gate electrode insulatively provided above said first base layer and a portion of said second base layer positioned between said first base layer and said second emitted layer, said first gate electrode forming a voltagecontrolled switching transistor together with said second emitter layer, said portion of said second base layer which serves as a channel region, and said first base layer; a second gate electrode formed on said second base layer; said second base layer comprising, a first heavily doped region defined in said second base layer so as to be electrically in direct contact with said second gate electrode, a lightly doped semiconductor region provided at least in said channel region of said transistor, and a second heavily doped region defined at a bottom section of said second base layer to be in contact with said first heavily doped region.
Claim 2
Dependent Claim
168 words
An insulated gate thyristor comprising: a first emitter layer; a first base layer; a second emitter layer; a second base layer having a bottom section; a first gate electrode insulatively provided above said first base layer and a portion of said second base layer positioned between said first base layer and said second emitted layer, said first gate electrode forming a voltagecontrolled switching transistor together with said second emitter layer, said portion of said second base layer which serves as a channel region, and said first base layer; a second gate electrode formed on said second base layer; said second base layer comprising, a first heavily doped region defined in said second base layer so as to be electrically in direct contact with said second gate electrode, a lightly doped semiconductor region provided at least in said channel region of said transistor, and a second heavily doped region defined at a bottom section of said second base layer to be in contact with said first heavily doped region.
Claim 3
Dependent Claim
31 words
The thyristor according to claim 1, wherein said lightly doped region is of the same conductivity type as said heavily doped layer and surrounds at least partially said second emitter layer.
Claim 4
Dependent Claim
40 words
The thyristor according to claim 2, further comprising: (h) a heavily doped semiconductive buffer layer provided between said first emitter layer and said first base layer and which has the same conductivity type as that of said first base layer.
Claim 5
Dependent Claim
21 words
The thyristor according to claim 3, wherein said buffer layer comprises a layer portion partly exposed through said first emitter layer.
Claim 6
Dependent Claim
24 words
The thyristor according to claim 4, further comprising: (i) a third gate electrode formed directly on a layer portion exposed from said buffer layer.
Claim 7
Dependent Claim
51 words
The thyristor according to claim 5, further comprising: (j) a first conductive layer formed on said first emitter layer for functioning as a first main electrode of said thyristor; and (k) a second conductive layer formed on said second emitter layer for functioning as a second main electrode of said thyristor.
Claim 8
Dependent Claim
17 words
The thyristor according to claim 6, wherein said transistor comprises a metal oxide semiconductor field effect transistor.
Claim 9
Dependent Claim
24 words
The thyristor according to claim 7, wherein said first main electrode is an anode electrode, and said second main electrode is a cathode electrode.
Claim 10
Dependent Claim
25 words
The thyristor according to claim 1, wherein said lightly doped region is in contact with said first heavily doped region in said second base layer.
Claim 11
Dependent Claim
20 words
The thyristor according to claim 9, wherein said lightly doped region has a depth greater than said second emitter layer.
Claim 12
Dependent Claim
29 words
The thyristor according to claim 10, wherein said second emitter layer is positioned in said lightly doped region so that said lightly doped region surrounds said second emitter layer.
Claim 13
Dependent Claim
20 words
The thyristor according to claim 9, wherein said lightly doped region has a depth less than said second emitter layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-24 | 1994-03-26 | 1994-09-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-24 | 1998-03-26 | 1998-09-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-24 | 2002-03-26 | 2002-09-25 | $7700.00 | Window Closed / Lapsed |