Thyristor with enhancement and depletion mode FET control for improved switch behavior and method of using same

Claim 1

A thyristor comprising a semiconductor body which exhibits an n-emitter contacted by a cathode electrode with an adjacent p-base layer and a p-emitter contacted by an anode electrode with an adjacent n-base layer, a plurality of controllable emitter short-circuits designed as MIS structures disposed at a boundary surface of the semiconductor body, said emitter short-circuits each including a first semiconductor region of a first conductivity type connected to one of said electrodes, a second semiconductor region of the first conductivity type connected to a base layer, and a third semiconductor area lying between said semiconductor regions and being covered by a gate electrically insulated from the semiconductor body, a first part of the MIS structures being of the depletion type and a second part of the MIS structures being of the enhancement type, a first common control terminal connected to the gates of the MIS structures of the one type, a second common control terminal connected to the gates of the MIS structures of the other type, one of said emitters including a plurality of emitter regions, and said first and second parts of the MIS structures together taking up between 10% and 80% of the total cross-sectional surface taken up by all of said emitter regions.