Patent US4958210A successfully refreshed from Google Patents.
US4958210A
Expired / Lapsed
US
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High voltage integrated circuits
Assignee: Intersil Corp
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Filing: 1989-11-20
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Granted: 1990-09-18
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Expires: 2009-11-20
Abstract
Abstract Premature avalanche breakdown resulting from high electric fields produced by metal interconnections crossing underlying high conductivity regions of an integrated circuit is eliminated by selectively providing discontinuities in the high conductivity regions underlying the metal interconnection paths.
Inventors
- 👤 Surinder Krishna
- 👤 Manuel L. Torreno, Jr.
- 👤 Michael S. Adler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:49
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/482; H10W20/484; H10D; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D64/00; H10D64/20; H10D64/23; H10D64/231
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
116 words
A monolithic integrated circuit including a semiconductor substrate with an epitaxial layer thereover, said layer having an active semiconductor device formed therein and electrically isolated from other devices in said layer, said active semiconductor device including electrode means insulatingly overlying said layer and conducting a selected region of said active semiconductor device, and a region of higher conductivity than said layer substantially enclosing said selected region except a region of lower conductivity lying substantially directly beneath said electrode means, said electrode means thereby not crossing said higher conductivity region and thereby avoiding premature avalanche breakdown in the semiconductor device of said monolithic integrated circuit upon application of bias voltages to said device via said electrode means.
Claim 2
Dependent Claim
116 words
A monolithic integrated circuit including a semiconductor substrate with an epitaxial layer thereover, said layer having an active semiconductor device formed therein and electrically isolated from other devices in said layer, said active semiconductor device including electrode means insulatingly overlying said layer and conducting a selected region of said active semiconductor device, and a region of higher conductivity than said layer substantially enclosing said selected region except a region of lower conductivity lying substantially directly beneath said electrode means, said electrode means thereby not crossing said higher conductivity region and thereby avoiding premature avalanche breakdown in the semiconductor device of said monolithic integrated circuit upon application of bias voltages to said device via said electrode means.
Claim 3
Dependent Claim
26 words
The monolithic integrated circuit of claim 1 wherein said active semiconductor device is a bipolar transistor having base, emitter and collector regions formed in said layer.
Claim 4
Dependent Claim
18 words
The monolithic integrated circuit of claim 2 wherein said electrode means contacts the base region of said transistor.
Claim 5
Dependent Claim
24 words
The monolithic integrated circuit of claim 3 further comprising a buried layer formed in said substrate, said higher conductivity region contacting said buried layer.
Claim 6
Dependent Claim
33 words
The monolithic integrated circuit of claim 4 wherein said higher conductivity region substantially encloses the base region of said bipolar transistor except in the portion of the semiconductor substrate underlying the electrode means.
Claim 7
Dependent Claim
20 words
The monolithic integrated circuit of claim 2 wherein said electrode means contacts the base and emitter regions of said transistor.
Claim 8
Dependent Claim
24 words
The monolithic integrated circuit of claim 6 further comprising a buried layer formed in said substrate, said higher conductivity region contacting said buried layer.
Claim 9
Dependent Claim
33 words
The monolithic integrated circuit of claim 7 wherein said higher conductivity region substantially encloses the base region of said bipolar transistor except in the portion of the semiconductor substrate underlying the electrode means.
Claim 10
Dependent Claim
18 words
The monolithic integrated circuit of claim 2 wherein said electrode means contacts the emitter region of said transistor.
Claim 11
Dependent Claim
24 words
The monolithic integrated circuit of claim 9 further comprising a buried layer formed in said substrate, said higher conductivity region contacting said buried layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-17 | 1994-03-19 | 1994-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-17 | 1998-03-19 | 1998-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-17 | 2002-03-19 | 2002-09-18 | $7700.00 | Window Closed / Lapsed |