US3751720A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Radially oriented monolithic circuit masterslice
Assignee: International Business Machines Corp
•
Filing: 1971-12-20
•
Granted: 1973-08-07
•
Expires: 1991-12-20
Abstract
Abstract A semiconductor integrated circuit masterslice comprising semiconductor substrate having a center of origin and arcuate or annular conductive lines thereon. A plurality of cell groups are symmetrically located on the semiconductor substrate with respect to radial lines extending from the center of origin so as to significantly increase packing densities compared to that available with orthongonally or randomly disposed monolithic integrated circuit structures.
Inventors
- 👤 W Nestork
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:51
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; H10W; H10W20/00; H10W20/20; H10W74/00; H10W74/10; H10W74/131
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
74 words
A semiconductor integrated circuit masterslice comprising: a. a semiconductor substrate having a center of origin, b. a plurality of annular conductive line means disposed over the surface of said semiconductor substrate, c. a plurality of sector cells having active and passive devices for performing independent logic functions disposed in said substrate around said center of origin, and d. means for connecting said plurality of sector cells to said plurality of annular conductive line means.
Claim 2
Dependent Claim
74 words
A semiconductor integrated circuit masterslice comprising: a. a semiconductor substrate having a center of origin, b. a plurality of annular conductive line means disposed over the surface of said semiconductor substrate, c. a plurality of sector cells having active and passive devices for performing independent logic functions disposed in said substrate around said center of origin, and d. means for connecting said plurality of sector cells to said plurality of annular conductive line means.
Claim 3
Dependent Claim
33 words
A semiconductor integrated circuit masterslice as in claim 1 wherein: a. said plurality of annular conductive line means comprise a plurality of separated concentric annular lines extending outwardly from said center of origin.
Claim 4
Dependent Claim
25 words
A semiconductor integrated circuit masterslice as in claim 2 wherein: a. said plurality of separated concentric annular lines comprise a plurality of arcuate metal rings.
Claim 5
Dependent Claim
32 words
A semiconductor integrated circuit masterslice as in claim 2 further including: a. subsurface connection means located below said semiconductor substrate surface and interconnecting at least some of said annular conductive line means.
Claim 6
Dependent Claim
75 words
A semiconductor integrated circuit masterslice as in claim 4 further including: a. additional interconnection metallurgy disposed at the same level as said plurality of separated concentric annular lines and extending in an intersecting direction thereto, and b. said subsurface connection means comprising a low resistivity underpass semiconductor region located in said semiconductor substrate for providing a bypass connection between at least one of said plurality of annular conductive line means and said additional interconnection metallurgy.
Claim 7
Dependent Claim
34 words
A semiconductor integrated circuit masterslice as in claim 4 further including: a. a plurality of separated radially disposed first semiconductor regions located in said substrate for providing interconnection paths between said plurality of cells.
Claim 8
Dependent Claim
34 words
A semiconductor integrated circuit masterslice as in claim 6 wherein: a. said active devices comprise an emitter region, and b. said first semiconductor regions comprise a semiconductor doped material corresponding to said emitter regions.
Claim 9
Dependent Claim
43 words
A semiconductor integrated circuit masterslice as in claim 1 further including: a. a plurality of separated second semiconductor regions, said second semiconductor regions comprising suitable doping levels for forming integrated circuit resistor passive devices and being adapted for interconnection to said active devices.
Claim 10
Dependent Claim
18 words
A semiconductor integrated circuit masterslice as in claim 8 wherein: a. said plurality of cells are sectorially shaped.
Claim 11
Dependent Claim
39 words
A semiconductor integrated circuit masterslice as in claim 6 wherein: a. said first first semiconductor regions are disposed around the perimeter of said masterslice and are adapted for interconnection to at least some of said annular conductive line means.
Claim 12
Dependent Claim
18 words
A semiconductor integrated circuit masterslice as in claim 8 wherein: a. said second semiconductor regions are sectorially shaped.
Claim 13
Dependent Claim
18 words
A semiconductor integrated circuit masterslice as in claim 10 wherein: a. said first semiconductor regions are sectorially shaped.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-08-06 | 1977-02-05 | 1977-08-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-08-06 | 1981-02-05 | 1981-08-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-08-06 | 1985-02-05 | 1985-08-07 | $7700.00 | Window Closed / Lapsed |