US4957875A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Vertical bipolar transistor
Assignee: International Business Machines Corp
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Filing: 1988-08-01
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Granted: 1990-09-18
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Expires: 2008-08-01
Abstract
Abstract A compressed vertical bipolar transistor configuration that eliminates one side of the standard symmetrical base contact, while also eliminating the requirement for a collector contact reach-thru. The bipolar transistor comprises: a collector layer; a base layer disposed over the collector layer; an emitter layer disposed over the base layer; a first sidewall insulating layer disposeed adjacent to and in contact with one side of the emitter layer, the base layer, and at least a portion of the collector layer; a second sidewall insulating layer disposed adjacent to and in contact with another side of the emitter layer and at least a portion of the base layer; and a base contact extension layer formed from heavily doped semiconductor material of the same conductivity type as the base layer, said base contact extension layer being in contact with and extending laterally from another side of the base layer. The structure further includes a base contact interconnect disposed on a surface of the base contact extension layer and; a collector contact extension layer formed from doped semiconductor material with the same conductivity type as the collector layer, with the collector contact extension layer being in contact with the collector layer and extending laterally from or below the one side thereof; and a collector contact interconnect disposed on a surface of the collector contact extension layer and separated from said emitter layer by only one or more insulating layers.
Inventors
- 👤 Shah Akbar
- 👤 Patricia L. Kroesen
- 👤 Seiki Ogura
- 👤 Nivo Rovedo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:05
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/40; H10D10/01; H10D10/051; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D62/17; H10D62/177; Y; Y10; Y10S; Y10S148/00; Y10S148/009; Y10S148/011
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
349 words
A method for forming a vertical bipolar transistor, comprising the steps of: obtaining a structure comprising a collector layer of doped semiconductor material, a base layer of doped semiconductor material disposed over said collector layer, an emitter layer of doped semiconductor material disposed over said base layer, a step of insulating material disposed over a first portion of the top surface of said emitter layer, but not over a second portion thereof, and a subcollector disposed below said collector layer in the region below said second portion of said top surface of said emitter layer; forming a sideway spacer of insulating material against the sidewall of said step to thereby cover a third portion of the top surface of said emitter layer, which third portion is less than said second portion; removing said emitter layer and at least a nominal portion of said base layer in a first volume adjacent to said sidewall spacer; removing said step; removing said emitter layer and at least a nominal portion of said base layer in a second volume below said removed step to expose said base layer and to provide a base contact surface, and also removing additional material in said first volume in order to expose a collector contact surface in said collector layer or said subcollector which is lower relative to said base contact surface; removing said sidewall spacer; forming simultaneously a first insulator sidewall in said first volume adjacent to and in contact with one side of said emitter layer, base layer and at least a nominal portion of said collector layer and touching said collector contact surface, and a second insulator sidewall in said second volume adjacent to and in contact with another side of said emitter layer and at least a nominal portion of said base layer, and touching said base contact surface; and forming a collector contact interconnect on surface and forming a base contact interconnect on the top surface of said exposed base contact surface, with said collector and base contact interconnects being separated from said emitter layer by only one or more insulator layers.
Claim 2
Independent Claim
349 words
A method for forming a vertical bipolar transistor, comprising the steps of: obtaining a structure comprising a collector layer of doped semiconductor material, a base layer of doped semiconductor material disposed over said collector layer, an emitter layer of doped semiconductor material disposed over said base layer, a step of insulating material disposed over a first portion of the top surface of said emitter layer, but not over a second portion thereof, and a subcollector disposed below said collector layer in the region below said second portion of said top surface of said emitter layer; forming a sideway spacer of insulating material against the sidewall of said step to thereby cover a third portion of the top surface of said emitter layer, which third portion is less than said second portion; removing said emitter layer and at least a nominal portion of said base layer in a first volume adjacent to said sidewall spacer; removing said step; removing said emitter layer and at least a nominal portion of said base layer in a second volume below said removed step to expose said base layer and to provide a base contact surface, and also removing additional material in said first volume in order to expose a collector contact surface in said collector layer or said subcollector which is lower relative to said base contact surface; removing said sidewall spacer; forming simultaneously a first insulator sidewall in said first volume adjacent to and in contact with one side of said emitter layer, base layer and at least a nominal portion of said collector layer and touching said collector contact surface, and a second insulator sidewall in said second volume adjacent to and in contact with another side of said emitter layer and at least a nominal portion of said base layer, and touching said base contact surface; and forming a collector contact interconnect on surface and forming a base contact interconnect on the top surface of said exposed base contact surface, with said collector and base contact interconnects being separated from said emitter layer by only one or more insulator layers.
Claim 3
Dependent Claim
33 words
A method as defined in claim 1, further comprising the step of increasing the concentration of the base dopant type in said exposed portion of said base layer below said base contact surface.
Claim 4
Dependent Claim
65 words
A method as defined in claim 1, further comprising the step of after said first-mentioned removing step, forming a very highly doped region in said first volume using a dopant having the same conductivity type as said collector layer; and during said third-mentioned removing step removing material in said first volume in order to expose said very highly doped region as the collector contact surface.
Claim 5
Dependent Claim
67 words
A method as defined in claim 1, wherein said first and second insulator sidewall forming step comprises the step of forming doped spacers, with a dopant conductivity type that is the same as the base dopant conductivity type; and heating, at some point in the process, to drive-in said dopant to the edge of said base layer adjacent to said insulator sidewalls, to prevent base edge inversion.
Claim 6
Dependent Claim
88 words
A method as defined in claim 3, further comprising the steps of: prior to the step of forming a very highly doped region in said first volume, adding dopant of the same conductivity type as said base layer to the material disposed below said first volume; and forming a third insulator sidewall laterally adjacent to and in contact with said sidewall spacer in said first volume so that a portion of said material in said first volume with said added dopant is disposed below said third insulator sidewall.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-17 | 1994-03-19 | 1994-09-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-17 | 1998-03-19 | 1998-09-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-17 | 2002-03-19 | 2002-09-18 | $7700.00 | Window Closed / Lapsed |