Non-volatile semiconductor memory having improved testing circuitry

Claim 1

A non-volatile semiconductor memory having a first node and a second node, the second node having a ground potential, comprising: a plurality of non-volatile memory cells each having a drain, a floating gate, a control gate, and a threshold potential, wherein data is written into a selected cell when the drain potential of the selected cell is at a predetermined normal writing voltage and a select signal is applied to the control gate of the selected cell; a plurality of bit lines, each memory cell being connected between one of the bit lines and said second node, each of said bit lines transferring data to and from associated memory cells; write voltage means for generating a first signal having the predetermined normal writing voltage and for supplying the first signal to the drain of at least one non-volatile memory cell when data is written into said at least one non-volatile memory cell; test voltage means for generating a second signal having a voltage equivalent to the predetermined normal writing voltage and for supplying the second signal to the drain of each non-volatile memory cell to simultaneously test all of the memory cells, said test voltage means including: circuit means, connected to the bit lines, for simultaneously testing all of the memory cells by supplying to the drain of each memory cell said second signal to detect changes in the threshold potential of each memory cell, said circuit means including a select transistor and a dummy cell, the select transistor of the circuit means and the dummy cell being connected in series between the first node and the second node.