Process for fabricating an integrated circuit

Claim 1

In a process for the manufacture of an integrated circuit including a lateral transistor arranged together with complimentary vertical bipolar transistors and CMOS field-effect transistors in a semiconductor body which is common to all components, and wherein the lateral transistor is comprised of two spaced regions of a first conductivity type, which constitute the emitter region and the collector region, incorporated into the surface of a semiconductor region of a second conductivity type, with the portion of the semiconductor region of the conductivity type located between the emitter and collector regions constituting the active base region of the transistor and with the active base region including a buried semiconductor zone which is disposed below and spaced from the surface, which extends to the emitter and collector regions, and which contains additional counterdoping impurities relative to the conductivity of the remaining surrounding portions of the active base region, thus concentrating the minority charge carriers in the active base region at a distance from the semiconductor surface between the emitter region and the collector region; the improvement comprising: simultaneously forming the buried semiconductor zone in the active base region of the lateral transistor and setting the threshold voltage of the CMOS field-effect transistors by ion implantation of charge carriers through a gate passivation layer covering the semiconductor surface.