Patent US4954944A successfully refreshed from Google Patents.
US4954944A
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Cache control circuit in cache memory unit with unit for enabling to reduce a read access time for cache memory
Assignee: NEC Corp
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Filing: 1988-04-22
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Granted: 1990-09-04
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Expires: 2008-04-22
Abstract
Abstract A cache control circuit in a cache memory unit having a cache memory in cooperation with an address conversion unit for converting a logical address into a physical address, a main memory, and a central processing unit. The central processing unit issues a control signal comprising a write/read request together with a logical address. The address conversion unit converts the logical address into the physical address which is applied to the cache memory unit. When the address conversion unit does not have a physical address corresponding to the logical address, the address conversion unit delivers a mismatch signal to the central processing unit and the cache control circuit to inform them of invalidation of the issued read/write request. The cache memory unit decides whether or not the physical address received is valid in the cache memory unit and produces a hit signal when it is valid. When the control signal has a read request as the read/write request, the cache control circuit produces a read access signal for carrying out the read operation prior to decision of the hit signal and the mismatch signal. Accordingly, the read access time to the cache memory is reduced. When the control signal has a write request as the read/write request, the cache control circuit produces a write access signal for writing data from the central processing unit into the cache memory after the decision of the hit signal and the non-mismatch signal is performed.
Inventors
- 👤 Sadanobu Ikeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 23:05
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1054
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
527 words
In a cache control circuit in a cache memory unit for use in cooperation with a main memory, a request source, and an address conversion unit, said request source producing a control signal comprising a read/write request together with a logical address comprising a first logical address portion and a second logical address portion, said address conversion unit converting said first logical address portion into a first physical address portion corresponding to said first logical address portion to produce said first physical address portion as a converted address signal at an output terminal when said address conversion unit has said first physical address portion corresponding to said first logical address portion, said address conversion unit producing a mismatch signal when said address conversion unit has no first physical address portion corresponding to said first logical address portion, said mismatch signal being delivered to said cache control circuit and said request source at a predetermined time duration after reception of said control signal, said request source deciding that said read/write request is invalid upon reception of said mismatch signal, said second logical address portion being directly applied to said cache memory unit as a second physical address portion without conversion, said cache memory unit comprising data memory means for temporarily holding a data block of data in said main memory which is currently used by said request source, control memory means for holding pairs of address tags and data memory addresses of said data block held in said data memory means, said control memory means being responsive to said second physical address portion producing one pair of said pairs of said address tags and said data memory addresses which correspond to said second physical address portion as a read address tag and a read data memory address, and comparing means coupled with said output terminal of said address conversion unit for comparing said read address tag with said converted output signal at said output terminal to deliver a hit signal to said cache control circuit when said read address tag is in conformity with said converted output signal, said cache control circuit receiving said control signal, said cache control circuit producing a read access signal for carrying out a read operation for said data memory means with use of said read data memory address when said read/write request of said control signal is a read request, said cache control circuit comprising: decoding means responsive to said control signal for decoding said control signal to extract said read request to produce a read request signal, said decoding means producing a start signal on reception of said control signal; timing generator means coupled to said decoding means and responsive to said start signal for sequentially generating timing signals at predetermined intervals; and means coupled with said decoding means and said timing generator means for producing said read access signal to said data memory means upon reception of both of said read request signal and a first one of said timing signals which is initially produced from said timing generator means, whereby a read operation for said data memory means starts without relation to said hit signal and said mismatch signal.
Claim 2
Dependent Claim
527 words
In a cache control circuit in a cache memory unit for use in cooperation with a main memory, a request source, and an address conversion unit, said request source producing a control signal comprising a read/write request together with a logical address comprising a first logical address portion and a second logical address portion, said address conversion unit converting said first logical address portion into a first physical address portion corresponding to said first logical address portion to produce said first physical address portion as a converted address signal at an output terminal when said address conversion unit has said first physical address portion corresponding to said first logical address portion, said address conversion unit producing a mismatch signal when said address conversion unit has no first physical address portion corresponding to said first logical address portion, said mismatch signal being delivered to said cache control circuit and said request source at a predetermined time duration after reception of said control signal, said request source deciding that said read/write request is invalid upon reception of said mismatch signal, said second logical address portion being directly applied to said cache memory unit as a second physical address portion without conversion, said cache memory unit comprising data memory means for temporarily holding a data block of data in said main memory which is currently used by said request source, control memory means for holding pairs of address tags and data memory addresses of said data block held in said data memory means, said control memory means being responsive to said second physical address portion producing one pair of said pairs of said address tags and said data memory addresses which correspond to said second physical address portion as a read address tag and a read data memory address, and comparing means coupled with said output terminal of said address conversion unit for comparing said read address tag with said converted output signal at said output terminal to deliver a hit signal to said cache control circuit when said read address tag is in conformity with said converted output signal, said cache control circuit receiving said control signal, said cache control circuit producing a read access signal for carrying out a read operation for said data memory means with use of said read data memory address when said read/write request of said control signal is a read request, said cache control circuit comprising: decoding means responsive to said control signal for decoding said control signal to extract said read request to produce a read request signal, said decoding means producing a start signal on reception of said control signal; timing generator means coupled to said decoding means and responsive to said start signal for sequentially generating timing signals at predetermined intervals; and means coupled with said decoding means and said timing generator means for producing said read access signal to said data memory means upon reception of both of said read request signal and a first one of said timing signals which is initially produced from said timing generator means, whereby a read operation for said data memory means starts without relation to said hit signal and said mismatch signal.
Claim 3
Dependent Claim
90 words
A cache control circuit as claimed in claim 1, which further comprises hit signal detecting means, coupled with said timing generator means, responsive to a second one of said timing signals which is later than said first one by a predetermined time interval for detecting whether or not said hit signal is delivered from said comparing means, said hit signal detecting means delivering a ready signal to said request source when said hit signal is detected, said request source entering a waiting condition in the absence of said ready signal.
Claim 4
Dependent Claim
89 words
A cache control circuit as claimed in claim 2, said cache memory unit further comprising means responsive to a main memory read request signal from said cache control circuit for accessing said main memory for reading, as a read block of data, data from an address in said main memory determined from said first and second physical address portions, wherein said cache control circuit further comprises means for generating said main memory read request signal when said hit signal is not detected in response to said second timing signal.
Claim 5
Dependent Claim
52 words
A cache control circuit as claimed in claim 3, which further comprises means for producing a write signal for writing said read block of data into said data memory means when said mismatch signal is not detected until said timing generator means generates another timing signal later than said second timing signal.
Claim 6
Dependent Claim
120 words
A cache control circuit as claimed in claim 2, said request source producing said control signal comprising a write request as said read/write request and data to be written, wherein said decoder means extracts said write request to produce a write request signal, said cache control circuit further comprising means responsive to said write request signal, said hit signal, and a third one of said timing signals which is later than said second one of said timing signals by a predetermined time interval for producing a write access signal to carry out a writing operation for said data to be written in said data memory means when said mismatch signal is not detected until occurrence of said third timing signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-03 | 1994-03-05 | 1994-09-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-03 | 1998-03-05 | 1998-09-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-03 | 2002-03-05 | 2002-09-04 | $7700.00 | Window Closed / Lapsed |