Patent US4953186A successfully refreshed from Google Patents.
US4953186A
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Phase jitter tracker
Assignee: Teridian Semiconductor Corp
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Filing: 1988-02-19
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Granted: 1990-08-28
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Expires: 2008-02-19
Abstract
Abstract The jitter tracker of the present invention uses a decision-directed error signal as an input to a feedback loop. The error signal is filtered and coupled to a phase locked loop centered at the center of the jitter tracking frequency range, which in the preferred embodiment is 55 Hz. The frequency width and center track and lock frequencies are set by a loop filter. A second order loop is used to acquire the frequency and phase jitter within an acceptable range. Once within this range, a first order loop is used to lock the amplitude to the input signal. The amplitude and phase values are subtracted from the incoming signal so that a new error may be calculated. In the preferred embodiment, the jitter tracker of the present invention is implemented in a digital signal processor. The jitter tracker of the preferred embodiment of the present invention comprises two filter loops. The first loop is used to generate the magnitude of the jitter error. The second loop generates the phase of the jitter error. The input to the jitter tracker is the quadrature portion of a normalized error term. This quadrature portion is multiplied by the cosine of the output of the error loops to generate the magnitude of the error signal. This term is multiplied by a scaling factor and is then integrated to generate a magnitude error term. The quadrature portion of the normalized error signal is multiplied in the second loop by the sine of the loop output. This phase error signal is coupled to a first order filter within a range in the preferred embodiment of plus or minus 10 Hz from a 55 Hz nominal frequency. The output of this first filter is multiplied by nominal 55 Hz vector and integrated to produce a phase error output. The real portion of this phase error signal is generated and combined with the magnitude error to produce a jitter correction factor for use in the receive channel circuitry.
Inventors
- 👤 Steve Levy
- 👤 Dave Hedberg
- 👤 Oscar Agazzi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:47
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/06; H04B1/10; H04B1/12; H04B1/123
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
206 words
A circuit for detecting and eliminating frequency jitter in an input signal comprising: sampling means for sampling said input signal and generating a normalized error signal; a first loop coupled to said normalized error signal for generating a magnitude component of said normalized error signal, said first loop comprising a first multiplier for multiplying said normalized error by a first factor to generate said magnitude component, said magnitude component coupled to a first integrator for generating a first error output signal; a second loop coupled to said normalized error signal for generating a phase component of said normalized error signal, said second loop comprising a second multiplier fo multiplying said normalized error by a second factor to generate said phase component, said phase component coupled to a first order filter for acquiring said phase component within a desired range and outputting a second error output signal, said second error output signal coupled to a second integrator for generating a third error output signal; a third multiplier coupled to said first error output signal, said third error output signal and a scaling factor for outputting a fourth error output signal for combining with said input signal at a combining means for eliminating jitter in said input signal.
Claim 2
Dependent Claim
206 words
A circuit for detecting and eliminating frequency jitter in an input signal comprising: sampling means for sampling said input signal and generating a normalized error signal; a first loop coupled to said normalized error signal for generating a magnitude component of said normalized error signal, said first loop comprising a first multiplier for multiplying said normalized error by a first factor to generate said magnitude component, said magnitude component coupled to a first integrator for generating a first error output signal; a second loop coupled to said normalized error signal for generating a phase component of said normalized error signal, said second loop comprising a second multiplier fo multiplying said normalized error by a second factor to generate said phase component, said phase component coupled to a first order filter for acquiring said phase component within a desired range and outputting a second error output signal, said second error output signal coupled to a second integrator for generating a third error output signal; a third multiplier coupled to said first error output signal, said third error output signal and a scaling factor for outputting a fourth error output signal for combining with said input signal at a combining means for eliminating jitter in said input signal.
Claim 3
Dependent Claim
18 words
The circuit of claim 1 wherein said first factor is the cosine of said third error output signal.
Claim 4
Dependent Claim
18 words
The circuit of claim 1 wherein said second factor is the sine of said third error output signal.
Claim 5
Dependent Claim
28 words
The circuit of claim 1 wherein said normalized error signal has a magnitude and phase component and said phase component is coupled to said first and second multipliers.
Claim 6
Dependent Claim
15 words
The circuit of claim 1 wherein said desired range is approximately 45 to 65 Hz.
Claim 7
Dependent Claim
38 words
The circuit of claim 1 further including an adder coupled to said second error output signal for adding a nominal frequency vector to said second error output signal, said adder having an output coupled to said second integrator.
Claim 8
Dependent Claim
17 words
The circuit of claim 6 wherein said nominal frequency vector has a frequency of approximately 55 Hz.
Claim 9
Dependent Claim
35 words
The circuit of claim 2 wherein said magnitude component is approximated by a real portion of a complex error signal and said phase component is approximated by an imaginary portion of said complex error signal.
Claim 10
Dependent Claim
227 words
A circuit for detecting and eliminating jitter from an input signal comprising: sampling means coupled to said input signal for sampling said input signal and generating a normalized error signal having an imaginary component; a first loop coupled to said imaginary component for generating a magnitude error of said imaginary component, said first loop having a first multiplier coupled to said imaginary component and to a first factor, said first multiplier having a first output, a first integrator coupled to said first output and outputting a second output; a second loop coupled to said imaginary component for generating a phase error of said imaginary component, said second loop having a second multiplier coupled to said imaginary component and to a second factor, said second multiplier having a third output, a first lowpass filter means coupled to said third output for acquiring said third output in a desired range, said filter means having a forth output, a first adder coupled to said fourth output and to a third factor, said first adder having a fifth output, a second integator coupled to said fifth output and outputting a sixth output; a third multiplier coupled to said second and sixth outputs and to a scaling factor, said third multiplier outputting a seventh signal for combining with said input signal at a combining means to eliminate jitter in said input signal.
Claim 11
Dependent Claim
227 words
A circuit for detecting and eliminating jitter from an input signal comprising: sampling means coupled to said input signal for sampling said input signal and generating a normalized error signal having an imaginary component; a first loop coupled to said imaginary component for generating a magnitude error of said imaginary component, said first loop having a first multiplier coupled to said imaginary component and to a first factor, said first multiplier having a first output, a first integrator coupled to said first output and outputting a second output; a second loop coupled to said imaginary component for generating a phase error of said imaginary component, said second loop having a second multiplier coupled to said imaginary component and to a second factor, said second multiplier having a third output, a first lowpass filter means coupled to said third output for acquiring said third output in a desired range, said filter means having a forth output, a first adder coupled to said fourth output and to a third factor, said first adder having a fifth output, a second integator coupled to said fifth output and outputting a sixth output; a third multiplier coupled to said second and sixth outputs and to a scaling factor, said third multiplier outputting a seventh signal for combining with said input signal at a combining means to eliminate jitter in said input signal.
Claim 12
Dependent Claim
16 words
The circuit of claim 9 wherein said first factor comprises the cosine of said sixth output.
Claim 13
Dependent Claim
16 words
The circuit of claim 9 wherein said second factor comprises the sine of said sixth output.
Claim 14
Dependent Claim
14 words
The circuit of claim 9 wherein said third factor comprises a nominal frequency vector.
Claim 15
Dependent Claim
17 words
The circuit of claim 12 wherein said nominal frequency vector has a frequency of approximately 55 Hz.
Claim 16
Dependent Claim
15 words
The circuit of claim 9 wherein said desired range is approximately 45 to 65 Hz.
Claim 17
Dependent Claim
134 words
A circuit for detecting and eliminating frequency jitter in an input signal comprising: a first phase locked loop coupled to said input signal for acquiring said frequency jitter and determining the magnitude of said frequency jitter; a second loop coupled to said input signal for acquiring the phase of said frequency jitter; a subtraction means coupled to said input signal, said first loop and said second loop for subtracting said phase and magnitude of said frequency jitter from said input signal to generate a first error signal; combining means coupled to said input signal and said subtraction means for combining said first error signal with said input signal; said first loop including sampling means coupled to said input signal for sampling said input signal and generating a normalized error signal having an imaginary component.
Claim 18
Dependent Claim
134 words
A circuit for detecting and eliminating frequency jitter in an input signal comprising: a first phase locked loop coupled to said input signal for acquiring said frequency jitter and determining the magnitude of said frequency jitter; a second loop coupled to said input signal for acquiring the phase of said frequency jitter; a subtraction means coupled to said input signal, said first loop and said second loop for subtracting said phase and magnitude of said frequency jitter from said input signal to generate a first error signal; combining means coupled to said input signal and said subtraction means for combining said first error signal with said input signal; said first loop including sampling means coupled to said input signal for sampling said input signal and generating a normalized error signal having an imaginary component.
Claim 19
Dependent Claim
21 words
The circuit of claim 15 wherein said magnitude component is coupled to a first integrator for generating a second output signal
Claim 20
Dependent Claim
53 words
The circuit of claim 15 wherein said second loop comprises a first multiplier for multiplying said normalized error by a first factor to generate said phase component, said phase component coupled to a first order filter for acquiring said phase component within a desired frequency range and outputting a third error output signal.
Claim 21
Dependent Claim
28 words
The circuit of claim 17 wherein said second loop further includes an integrating means coupled to said third error output signal for generating a fourth error output signal.
Claim 22
Independent Claim
103 words
A method for detecting and eliminating frequency jitter in an input signal comprising the steps of: receiving said input signal and determining a magnitude of said frequency jitter wherein said step of determining said magnitude comprises generating a normalized error signal and providing said normalized error signal to first order loop to generate said magnitude of said frequency jitter; determining a phase of said frequency jitter; generating a first error signal by subtracting said phase and amplitude of said frequency jitter from said input signal; combining said first error signal with said input signal to remove said frequency jitter from said input signal.
Claim 23
Independent Claim
103 words
A method for detecting and eliminating frequency jitter in an input signal comprising the steps of: receiving said input signal and determining a magnitude of said frequency jitter wherein said step of determining said magnitude comprises generating a normalized error signal and providing said normalized error signal to first order loop to generate said magnitude of said frequency jitter; determining a phase of said frequency jitter; generating a first error signal by subtracting said phase and amplitude of said frequency jitter from said input signal; combining said first error signal with said input signal to remove said frequency jitter from said input signal.
Claim 24
Dependent Claim
30 words
The method of claim 19 wherein said step of determining said phase of said frequency jitter comprises multiplying said normalized error signal by a first factor to generate said phase.
Claim 25
Dependent Claim
159 words
A circuit for detecting and eliminating frequency jitter in an input signal comprising: a first phase locked loop coupled to said input signal for acquiring said frequency jitter and determining a magnitude component of an imaginary component of said frequency jitter; a second loop coupled to said input signal for acquiring the phase of said frequency jitter; a subtraction means coupled to said input signal, said first loop and said second loop for subtracting said phase and amplitude of said frequency jitter from said input signal to generate a first error signal; a combining means coupled to said input signal and said subtraction means for combining said first error signal with said input signal; said first loop including sampling means coupled to said input signal for sampling said input signal and generating a normalized error signal having said imaginary component, and further including a first order filter loop coupled to said normalized error signal for generating said magnitude component.
Claim 26
Dependent Claim
159 words
A circuit for detecting and eliminating frequency jitter in an input signal comprising: a first phase locked loop coupled to said input signal for acquiring said frequency jitter and determining a magnitude component of an imaginary component of said frequency jitter; a second loop coupled to said input signal for acquiring the phase of said frequency jitter; a subtraction means coupled to said input signal, said first loop and said second loop for subtracting said phase and amplitude of said frequency jitter from said input signal to generate a first error signal; a combining means coupled to said input signal and said subtraction means for combining said first error signal with said input signal; said first loop including sampling means coupled to said input signal for sampling said input signal and generating a normalized error signal having said imaginary component, and further including a first order filter loop coupled to said normalized error signal for generating said magnitude component.
Claim 27
Dependent Claim
21 words
The circuit of claim 21 wherein said magnitude component is coupled to a first integrator for generating a second output signal.
Claim 28
Dependent Claim
53 words
The circuit of claim 21 wherein said second loop comprises a first multiplier for multiplying said normalized error by a first factor to generate said phase component, said phase component coupled to a first order filter for acquiring said phase component within a desired frequency range and outputting a third error output signal.
Claim 29
Dependent Claim
28 words
The circuit of claim 23 wherein said second loop further includes an integrating means coupled to said third error output signal for generating a fourth error output signal.
Claim 30
Independent Claim
108 words
A method for detecting and eliminating frequency jitter in an input signal comprising the steps of: receiving said input signal and detemining a magnitude of an imaginary component of said frequency jitter wherein said step of determining said magnitude comprises generating a normalized error signal and providing said normalized error signal to a first order loop to generate said magnitude of said imaginary component; determining a phase of said frequency jitter; generating a first error signal by subtracting said phase and amplitude of said frequency jitter from said input signal; combining said first error signal with said input signal to remove said frequency jitter from said input signal.
Claim 31
Independent Claim
108 words
A method for detecting and eliminating frequency jitter in an input signal comprising the steps of: receiving said input signal and detemining a magnitude of an imaginary component of said frequency jitter wherein said step of determining said magnitude comprises generating a normalized error signal and providing said normalized error signal to a first order loop to generate said magnitude of said imaginary component; determining a phase of said frequency jitter; generating a first error signal by subtracting said phase and amplitude of said frequency jitter from said input signal; combining said first error signal with said input signal to remove said frequency jitter from said input signal.
Claim 32
Dependent Claim
30 words
The method of claim 25 wherein said step of determining said phase of said frequency jitter comprises multiplying said normalized error signal by a first factor to generate said phase.
References Cited (Backward Citations)
US3878468A
Cited
US4032847A
Cited
US4349916A
Cited
US4458355A
Cited
US4569064A
Cited
US4475214A
Cited
US4590602A
Cited
US4639682A
Cited
US4631738A
Cited
US4633485A
Cited
US4683578A
Cited
US4689804A
Cited
US4689805A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-08-27 | 1994-02-26 | 1994-08-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-27 | 1998-02-26 | 1998-08-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-27 | 2002-02-26 | 2002-08-28 | $7700.00 | Window Closed / Lapsed |