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US4639682A Expired / Lapsed US ⏱️ 0.0 years remaining

Carrier reproducing circuit for phase shift keying signals

Assignee: Toshiba Corp
•
Filing: 1985-07-02
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Granted: 1987-01-27
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Expires: 2005-07-02
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Abstract

Abstract A frequency converter converts the frequency of a PSK signal into a frequency of a carrier to be reproduced. A carrier reproducing circuit including a PLL circuit reproduces the carrier. The intended data contained in the reproduced carrier is demodulated. A frequency correction data generator forms correction data according to a bit error rate of the demodulated data, and superposes the correction data on a control voltage to a voltage controlled oscillator of the PLL circuit.

Inventors

  • 👤 Seiji Takeuchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 21:05
CPC Classifications
H; H03; H03K; H03K9/00; H03K9/04; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2272

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 190 words
A carrier reproducing circuit for signals transmitted in carrier suppressed modulation comprising: frequency converting means for converting said transmission signal to a frequency of a carrier to be reproduced; demodulator means, coupled to said frequency converting means, for demodulating transmission data, said demodulator means including carrier reproducing means for producing said carrier, voltage controlled oscillator means, coupled to said carrier reproducing means, for generating an oscillation output and for supplying said oscillation output to said carrier reproducing means, and phase comparing means, coupled to said carrier reproducing means and said voltage controlled oscillator means, for comparing the phase of said reproduced carrier and said oscillation output and for generating a control voltage, said voltage controlled oscillator means being controlled by said control voltage; error detecting means coupled to said demodulator means for detecting the bit error rate of said demodulated data; and frequency correction data generator means coupled to said error detecting means for generating a correction voltage in accordance with said detected bit error rate, said frequency correction data generator being coupled to said voltage controlled oscillator means so as to superimpose said correction voltage onto said control voltage.
Claim 2
Dependent Claim 190 words
A carrier reproducing circuit for signals transmitted in carrier suppressed modulation comprising: frequency converting means for converting said transmission signal to a frequency of a carrier to be reproduced; demodulator means, coupled to said frequency converting means, for demodulating transmission data, said demodulator means including carrier reproducing means for producing said carrier, voltage controlled oscillator means, coupled to said carrier reproducing means, for generating an oscillation output and for supplying said oscillation output to said carrier reproducing means, and phase comparing means, coupled to said carrier reproducing means and said voltage controlled oscillator means, for comparing the phase of said reproduced carrier and said oscillation output and for generating a control voltage, said voltage controlled oscillator means being controlled by said control voltage; error detecting means coupled to said demodulator means for detecting the bit error rate of said demodulated data; and frequency correction data generator means coupled to said error detecting means for generating a correction voltage in accordance with said detected bit error rate, said frequency correction data generator being coupled to said voltage controlled oscillator means so as to superimpose said correction voltage onto said control voltage.
Claim 3
Dependent Claim 18 words
A carrier reproducing circuit according to claim 1, wherein said transmission signal includes a 4-phase shift keying signal.
Claim 4
Dependent Claim 23 words
A carrier reproducing circuit according to claim 1, wherein the output of said voltage controlled oscillator means couples to said frequency converting means.
Claim 5
Dependent Claim 20 words
A carrier reproducing circuit according to claim 1, wherein said error detecting means includes a Bose-Chaudhuri-Hocquengham (BCH) code correction circuit.
Claim 6
Dependent Claim 54 words
A carrier reproducing circuit according to claim 4, wherein said frequency correction data generator means includes counter means for counting the number of error detections generated by said BCH code correction circuit, said counter generating a count output, and pulse width modulator means for generating said correction voltage in accordance with said counter output.

References Cited (Backward Citations)

US4330861A Cited
US4525676A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-01-26 1990-07-28 1991-01-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-01-26 1994-07-28 1995-01-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-01-26 1998-07-28 1999-01-27 $7700.00 Window Closed / Lapsed

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