Accelerated data transfer mechanism using modified clock cycle

Claim 1

A data processing system having multiple logical devices including a first logical device, a second logical device and a third logical device, with the data processing system having a conventional machine clock cycle for normal operation and a modified clock cycle for transferring clocked electronic data between the first and the second logical device, the improvement comprising: a system clock generator for providing the conventional machine clock cycle of a predetermined time interval; controlling means for controlling the rate of data transfer between said first logical device and said second logical device, said controlling means connected to receive inputs from said clock generator and including timing logic means for generating the modified clock cycle which constitutes a shortened clock cycle which is not half a machine cycle; gating means connected from said timing logic means to said first and second logical devices for allowing said first and second logical devices to accept data or to send data during the modified clock cycle which is a fractional part of the machine cycle; and wherein said timing logic means comprises a multi-phase device connected to said system clock generator for receiving clock signal inputs at a first rate of even number of pulses per clock cycle, said multi-phase device generating an output clock signal at a second rate of odd number of pulses per clock cycle with said even number and odd number of pulses having the same frequency and being in phase with each other, said odd number of pulses per clock cycle constituting the aforesaid shortened clock cycle thereby providing accelerated data transfer during such shortened clock cycle while alternatively allowing data transfers with said third logical device during the conventional clock cycle.