US4713751A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Masking commands for a second processor when a first processor requires a flushing operation in a multiprocessor system
Assignee: International Business Machines Corp
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Filing: 1984-10-24
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Granted: 1987-12-15
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Expires: 2004-10-24
Abstract
Abstract A masking circuit for a multiprocessor system is disclosed. The masking circuit senses the existence and type of commands stored in the command status registers associated with the system processors. Masking begins if it is determined that information needed by one processor is located in the cache memory of another processor and is to be flushed to the main memory, which is accessible by the first processor. The masking circuit masks the command present in the command status register associated with the first processor, for the first processor to access the main memory, until after the information has been flushed from the cache to the main memory. The first processor is thus prevented from accessing the main memory until after the information has been flushed thereto.
Inventors
- 👤 Patrick F. Dutton
- 👤 Earl W. Jackson, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 17:07
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
247 words
A multiprocessor system comprising: a memory; a first processor connected to said memory, said first processor storing data therein; a first command status register connected to said first processor, said first command status register for storing normal command information for the execution of instructions by said first processor and flushing command information for the execution of instructions by a second processor; said second processor connected to said memory and to said first processor, said seocnd processor requiring access to said data in said first processor to execute an instruction, said second processor causing said first processor to store flushing command information in said first command status register upon the detection of said data in said first processor; a second command status register connected to said second processor, said second command status register storing normal command information for the execution of instructions by said seocnd processor; a memory control circuit connected to said memory, said first and said second processor, and said first and said second command status registers, said memory control circuit transferring data between said memory and said first processor in response to said normal command information in said first command status register during the execution of instructions by said first processor, and flushing said data in said first processor to said memory and masking normal command information in said second command status register in response to said flushing command information in said first command status register during the execution of instructions by said second processor.
Claim 2
Dependent Claim
247 words
A multiprocessor system comprising: a memory; a first processor connected to said memory, said first processor storing data therein; a first command status register connected to said first processor, said first command status register for storing normal command information for the execution of instructions by said first processor and flushing command information for the execution of instructions by a second processor; said second processor connected to said memory and to said first processor, said seocnd processor requiring access to said data in said first processor to execute an instruction, said second processor causing said first processor to store flushing command information in said first command status register upon the detection of said data in said first processor; a second command status register connected to said second processor, said second command status register storing normal command information for the execution of instructions by said seocnd processor; a memory control circuit connected to said memory, said first and said second processor, and said first and said second command status registers, said memory control circuit transferring data between said memory and said first processor in response to said normal command information in said first command status register during the execution of instructions by said first processor, and flushing said data in said first processor to said memory and masking normal command information in said second command status register in response to said flushing command information in said first command status register during the execution of instructions by said second processor.
Claim 3
Dependent Claim
44 words
The multiprocessor system of claim 1 wherein said memory control circuit clears said first command status register and unmasks said normal command information in said second command status register in response to the flushing of said data in said first processor to said memory.
Claim 4
Dependent Claim
42 words
The multiprocessor system of claim 1 wherein said memory control circuit transfers data between said memory and said second processor in response to said normal command information in said second command status register during the execution of instructions by said second processor.
Claim 5
Independent Claim
253 words
A method of efficiently using command status registers for transferring data between a memory and processors in a multiprocessor system, said multiprocessor system operating in normal mode when the data required by a processor to execute an instruction is located in the respective processor or in said memory, said multiprocessor system operating in flushing mode when the data required by a processor to execute an instruction is located in another processor, said operation in normal mode comprising the steps of: locating the data required for the excution of instructions by a first processor and locating the data required for the execution of instructions by a second processor; transferring the data required for the execution of instructions by said first processor between said memroy and said first processor in response to normal command information in a first command status register and transferring the data required for the execution of instructions by said second processor between said memory and said second processor in response to normal command information in a second command status register; said operation in flushing mode comprising the steps of: locating the data required for the execution of instructions by said second processor in said first processor; storing flushing command information in said first command status register; and, flushing the data required for the execution of instructions by said second processor from said first processor to said memory and masking normal command information in said second command status register in response to the flushing command information in said first command status register.
Claim 6
Independent Claim
253 words
A method of efficiently using command status registers for transferring data between a memory and processors in a multiprocessor system, said multiprocessor system operating in normal mode when the data required by a processor to execute an instruction is located in the respective processor or in said memory, said multiprocessor system operating in flushing mode when the data required by a processor to execute an instruction is located in another processor, said operation in normal mode comprising the steps of: locating the data required for the excution of instructions by a first processor and locating the data required for the execution of instructions by a second processor; transferring the data required for the execution of instructions by said first processor between said memroy and said first processor in response to normal command information in a first command status register and transferring the data required for the execution of instructions by said second processor between said memory and said second processor in response to normal command information in a second command status register; said operation in flushing mode comprising the steps of: locating the data required for the execution of instructions by said second processor in said first processor; storing flushing command information in said first command status register; and, flushing the data required for the execution of instructions by said second processor from said first processor to said memory and masking normal command information in said second command status register in response to the flushing command information in said first command status register.
Claim 7
Dependent Claim
57 words
The method of claim 4 further comprising the flushing mode step of: clearing said first command status register of the flushing command information and unmasking the normal command information in said second command status register after the data required for the execution of instructions by said second processor is flushed from said first processor to said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-14 | 1991-06-15 | 1991-12-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-14 | 1995-06-15 | 1995-12-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-14 | 1999-06-15 | 1999-12-15 | $7700.00 | Window Closed / Lapsed |