US4951103A
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US
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Fast, trench isolated, planar flash EEPROMS with silicided bitlines
Assignee: Texas Instruments Inc
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Filing: 1988-06-03
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Granted: 1990-08-21
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Expires: 2008-06-03
Abstract
Abstract A non-volatie cross-point memory cell array comprises a trench isolated cross-point array of memory cells (10), which are electrically programmable and electrically FLASH eraseable, having diffused regions (28) operable as bitlines, each diffused region (28) traversed by a plurality of control gates (54) operable as wordlines. The diffused regions (28) undergo a silicidation process to decrease their resistivity, and thereby increase the speed of the memory cell array. A tunnel oxide (18) is provided for electrical erasing and programming. Planarized, high quality insulating regions (40, 36), such as dichlorosilane oxide, buttress the floating gate (20) to isolate the bitlines form the wordlines and to improve isolation between the pass gate and the floating gate. A planar structure of the memory cell (10) provides flat topography ideal for three dimensional stacked structures. Trench isolation regions (56) reduce bitline capacitance, thereby increasing programming speed.
Inventors
- 👤 Agerico L. Esquivel
- 👤 Allan T. Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:50
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
171 words
A nonvolatile memory cell, comprising: a substrate having a first conductivity type; a first diffusion formed in said substrate adjacent to a surface of said substrate, said first diffusion having a second conductivity type; a second diffusion formed in said substrate adjacent to said surface of said substrate, said second diffusion having said second conductivity type and being spaced from said first diffusion defining a channel region therebetween; a first insulating layer formed on a first portion of said channel region, said first insulating layer extending from said first diffusion, but not extending to said second diffusion; a floating gate formed on said first insulating layer; a second insulating layer formed on a second portion of said channel region, said second insulating layer extending from said second diffusion to an edge of said first insulating layer; a pass gate formed on said second insulating layer; a third insulating layer formed on said floating gate; and a wordline formed in conductive contact with said pass gate and on said third insulating layer.
Claim 2
Dependent Claim
171 words
A nonvolatile memory cell, comprising: a substrate having a first conductivity type; a first diffusion formed in said substrate adjacent to a surface of said substrate, said first diffusion having a second conductivity type; a second diffusion formed in said substrate adjacent to said surface of said substrate, said second diffusion having said second conductivity type and being spaced from said first diffusion defining a channel region therebetween; a first insulating layer formed on a first portion of said channel region, said first insulating layer extending from said first diffusion, but not extending to said second diffusion; a floating gate formed on said first insulating layer; a second insulating layer formed on a second portion of said channel region, said second insulating layer extending from said second diffusion to an edge of said first insulating layer; a pass gate formed on said second insulating layer; a third insulating layer formed on said floating gate; and a wordline formed in conductive contact with said pass gate and on said third insulating layer.
Claim 3
Dependent Claim
20 words
A nonvolatile memory cell as in claim 1 wherein said first insulating layer is thinner than said second insulating layer.
Claim 4
Dependent Claim
18 words
A nonvolatile memory cell as in claim 1 wherein said first and second insulting layers comprise silicon dioxide.
Claim 5
Dependent Claim
18 words
A nonvolatile memory cell as in claim 3 where said first insulating layer has a thickness of 100Å.
Claim 6
Dependent Claim
26 words
A nonvolatile memory cell as in claim 1 where the top of said pass gate and the top of said third insulating layer are substantially coplanar.
Claim 7
Dependent Claim
30 words
A nonvolatile memory cell as in claim 1 wherein said first insulating layer comprises a first portion and a second portion, said first portion being thinner than said second portion.
Claim 8
Dependent Claim
37 words
A nonvolatile memory cell as in claim 1 further comprising: a first metal silicide layer formed on a surface of said first diffusion; and a second metal silicide layer formed on a surface of said second diffusion.
Claim 9
Dependent Claim
209 words
A nonvolatile memory array, comprising: a substrate having a firs conductivity type; a plurality of diffusions formed in said substrate adjacent to a surface of said substrate, said plurality of diffusions formed in parallel strip-s, each of said diffusions separated by a channel region between said strips, and each of said diffusions having a second conductivity type; a plurality of wordlines formed on said substrate, said plurality of wordlines formed in strips running perpendicular to said plurality of diffusions; a plurality of memory cells, each of said memory cells comprising: a first insulating layer formed on a first portion of said channel region, said first insulating layer extending from one of said diffusions, but no extending to a neighboring diffusion of one of said diffusions; a floating gate formed on said first insulating layer; a second insulating layer formed on a second portion of said channel region, said second insulating layer extending from said neighboring diffusion to an edge of said first insulating layer opposite said one of said diffusions; a pass gate formed on said second insulating layer, said pass gate in electrical contact with at least one of said wordlines; and a third insulating layer interposed between said floating gate and at least one of said wordlines.
Claim 10
Dependent Claim
209 words
A nonvolatile memory array, comprising: a substrate having a firs conductivity type; a plurality of diffusions formed in said substrate adjacent to a surface of said substrate, said plurality of diffusions formed in parallel strip-s, each of said diffusions separated by a channel region between said strips, and each of said diffusions having a second conductivity type; a plurality of wordlines formed on said substrate, said plurality of wordlines formed in strips running perpendicular to said plurality of diffusions; a plurality of memory cells, each of said memory cells comprising: a first insulating layer formed on a first portion of said channel region, said first insulating layer extending from one of said diffusions, but no extending to a neighboring diffusion of one of said diffusions; a floating gate formed on said first insulating layer; a second insulating layer formed on a second portion of said channel region, said second insulating layer extending from said neighboring diffusion to an edge of said first insulating layer opposite said one of said diffusions; a pass gate formed on said second insulating layer, said pass gate in electrical contact with at least one of said wordlines; and a third insulating layer interposed between said floating gate and at least one of said wordlines.
Claim 11
Dependent Claim
20 words
A nonvolatile memory array as in claim 8 wherein said first insulating layer is thinner than said second insulating layer.
Claim 12
Dependent Claim
17 words
A nonvolatile array as in claim 8 where said first and second insulating layers comprise silicon dioxide.
Claim 13
Dependent Claim
18 words
A nonvolatile memory array as in claim 10 where said first insulating layer has a thickness of 100Å.
Claim 14
Dependent Claim
26 words
A nonvolatile memory array as in claim 8 where the top of said pass gate and the top of said third insulting layer are substantially coplanar.
Claim 15
Dependent Claim
30 words
A nonvolatile memory array as in claim 8 wherein said first insulating layer comprises a first portion and a second portion, said first portion being thinner than said second portion.
Claim 16
Dependent Claim
25 words
A nonvolatile memory array as in claim 8 further comprising a plurality of metal silicide layers formed on a surface of aid plurality of diffusions.
Claim 17
Dependent Claim
46 words
A nonvolatile memory array as in claim 8 further comprising a plurality of insulating layers formed on the surface of said plurality of diffusions, the top surface of plurality of insulating layers being substantially coplanar with said first insulating layer of said plurality of memory cells.
Claim 18
Dependent Claim
48 words
A nonvolatile memory array as in claim 14 further comprising a plurality of insulating layers formed on the surface of said plurality of metal silicide layers, the top surface of plurality of insulating layers being substantially coplanar with said third insulating layer of said plurality of memory cells.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-20 | 1994-02-19 | 1994-08-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-20 | 1998-02-19 | 1998-08-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-20 | 2002-02-19 | 2002-08-21 | $7700.00 | Window Closed / Lapsed |