Abstract This invention provides a method for fabricating a semiconductor device comprising the steps of forming buried layers on the silicon substrate; etching an epitaxial layer after said layer is grown up, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed remained the same thickness as grown up; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor. High efficiency and high integration is easily attained in fabricating the high speed bipolar transistor and high performance CMOS transistor on same chip and by reducing the difficulty in processing according to the method of present invention.
A method for fabricating a semiconductor device comprising the steps of: forming buried layers on the silicon substrate; etching an epitaxial after said layer is grown, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed the same thickness as grown; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor.
Claim 2
Independent Claim
86 words
A method for fabricating a semiconductor device comprising the steps of: forming buried layers on the silicon substrate; etching an epitaxial after said layer is grown, the step further including the processes of etching selectively the silicon epitaxial layer of well region on which a high speed bipolar transistor is formed to be thin and keeping the silicon epitaxial layer of well region on which nMOS transistor is formed the same thickness as grown; and forming a pMOS transistor, a nMOS transistor and a bipolar transistor.
Claim 3
Dependent Claim
43 words
A method according to claim 1, wherein the p-type well region 16 is implanted with column III impurities through the nitride mask opening and the n-type well region 15 is defined by the oxide layer 9 etching after the p-type well 16 formation.