US4949247A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for transferring multiple vector data elements to and from vector memory in a single operation
Assignee: Stardent Computer Inc
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Filing: 1988-02-23
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Granted: 1990-08-14
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Expires: 2008-02-23
Abstract
Abstract Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data elements for use by the processor, the vector memory having a port for reading and writing, and at least one staging register interposed between the vector memory port and the processor; the port and the register are each sufficiently wide to span more than one data element. As a result, on average fewer than one read or write operation per data element is required to access the vector memory via the port. Access to the vector memory port (i.e., a shared resource) is managed between a number of users by preassigning each user time slots that occur from time to time in each of which only one user is premitted to request access to the vector memory port, establishing a nominal priority ranking of types of requests made by the users for governing the order in which the users will be served, providing an arbitration mechanism for resolving conflicting requests by the users for access to the vector memory port based on the types of requests, and modifying the nominal priority ranking to temporarily lower the priority of a type of request made by a user that has previously been given access to the vector memory port as a result of the arbitration mechanism but has been unable to execute the access.
Inventors
- 👤 R. Ashley Stephenson
- 👤 Kevin B. Normoyle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:32
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8061; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3836; G06F9/3851
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
112 words
Apparatus for performing vector operations on the data elements of vector comprising a vector processor for performing operations on said elements, a vector memory for storing said data elements for use by said processor, said vector memory having a port for reading and writing, and at least one staging register interposed between said vector memory port and said processor, said port and said register each being sufficiently wide to span more than one said data element, whereby on average fewer than one read or write operation per data element is required to access said vector memory via said port to transfer multiple data elements between said vector memory and said staging register.
Claim 2
Dependent Claim
112 words
Apparatus for performing vector operations on the data elements of vector comprising a vector processor for performing operations on said elements, a vector memory for storing said data elements for use by said processor, said vector memory having a port for reading and writing, and at least one staging register interposed between said vector memory port and said processor, said port and said register each being sufficiently wide to span more than one said data element, whereby on average fewer than one read or write operation per data element is required to access said vector memory via said port to transfer multiple data elements between said vector memory and said staging register.
Claim 3
Dependent Claim
14 words
The apparatus of claim 1 wherein said vector memory has a single said port.
Claim 4
Dependent Claim
15 words
The apparatus of claim 1 wherein said vector memory includes a plurality of said ports.
Claim 5
Dependent Claim
49 words
The apparatus of claim 1 wherein each line of memory in said vector memory contains multiple data elements, and said staging register is capable of containing multiple data elements, whereby said multiple data elements are transferred between a line of memory and said staging register in a single access.
Claim 6
Dependent Claim
151 words
The apparatus of claim 1 wherein each line of memory contains multiple operand and result data elements, and further comprising operand staging registers, each capable of containing multiple operand data elements. a controller for causing multiple operand data elements to be transferred from a line of said vector memory to a first operand staging register in a first single access, and causing multiple operand data elements to be transferred from a line of said vector memory to a second operand staging register in a second single access, said vector processor operating on the operand data elements in said first and second operand staging registers and generating result data elements, and a result staging register for storing multiple result data elements from said processor, said controller causing said multiple result data elements to be transferred from said result staging register to a line of said vector memory in a third single access.
Claim 7
Dependent Claim
61 words
The apparatus of claim 5 further comprising a multiplexer, responsive to control signals from said controller, for transferring a selected one of the multiple operand data elements from one of said operand staging registers to said vector processor and for transferring a result data element from said vector processor to a selected one of multiple locations in said result staging register.
Claim 8
Dependent Claim
16 words
The apparatus of claim 1 wherein said operations performed by said vector processor are arithmetic operations.
Claim 9
Independent Claim
107 words
A method of performing vector operations on the data elements of vectors, comprising storing said data elements in a vector memory for use by a vector processor which performs operations on said elements, said vector memory having a port for reading and writing, and transferring said data elements between said vector memory and at least one staging register that is interposed between said vector memory port and said processor, said port and said register each being sufficiently wide to span more than one said data element so that on average fewer than one read or write operation is required to access said vector memory via said port.
Claim 10
Independent Claim
107 words
A method of performing vector operations on the data elements of vectors, comprising storing said data elements in a vector memory for use by a vector processor which performs operations on said elements, said vector memory having a port for reading and writing, and transferring said data elements between said vector memory and at least one staging register that is interposed between said vector memory port and said processor, said port and said register each being sufficiently wide to span more than one said data element so that on average fewer than one read or write operation is required to access said vector memory via said port.
Claim 11
Dependent Claim
16 words
The method of claim 8 wherein said operations performed by said vector processor are arithmetic operations.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-08-13 | 1994-02-12 | 1994-08-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-08-13 | 1998-02-12 | 1998-08-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-08-13 | 2002-02-12 | 2002-08-14 | $7700.00 | Window Closed / Lapsed |