US4766535A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-performance multiple port memory
Assignee: International Business Machines Corp
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Filing: 1985-12-20
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Granted: 1988-08-23
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Expires: 2005-12-20
Abstract
Abstract Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle. The pointer directs memory accessing to prevent conflicts. Conflicts are always avoided because one bank in each of the r groups is directed to supply data in response to a read address and the w remaining banks are available for writing data in response to the w write addresses redundantly so that each of the groups of memory banks will have valid data in at least one of its w+1 memory banks for a given address.
Inventors
- 👤 Daniel J. Auerbach
- 👤 Tien C. Chen
- 👤 Wolfgang J. Paul
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/3012; G06F9/30138; G06F15/00; G06F15/76; G06F15/80; G06F15/8053
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
230 words
A memory apparatus, responsive to first, second and third addresses supplied within an instruction cycle from respective address registers, for supplying data read from the first and second addresses to output registers and for writing data received from an input register to the third address, comprising: a first group of two memory banks, responsive at a predetermined time in the instruction cycle to the first address and the third address, for supplying data read from the first address in one of the two banks of said first group and for writing data received to the third address in the other bank of said first group; a second group of two memory banks, responsive to the second address and the third address at said predetermined time, for supplying data read from the second address in one of the two banks of said second group and for writing data received to the third address in the other bank of the two banks of said second group; and pointer means for each group for controlling the two banks of each group so that the one of the two banks in one of said groups then containing valid data is read while data is written to the other bank of the same group in each cycle, valid data being the latest data written, as denoted by what had been stored in said pointer means.
Claim 2
Dependent Claim
230 words
A memory apparatus, responsive to first, second and third addresses supplied within an instruction cycle from respective address registers, for supplying data read from the first and second addresses to output registers and for writing data received from an input register to the third address, comprising: a first group of two memory banks, responsive at a predetermined time in the instruction cycle to the first address and the third address, for supplying data read from the first address in one of the two banks of said first group and for writing data received to the third address in the other bank of said first group; a second group of two memory banks, responsive to the second address and the third address at said predetermined time, for supplying data read from the second address in one of the two banks of said second group and for writing data received to the third address in the other bank of the two banks of said second group; and pointer means for each group for controlling the two banks of each group so that the one of the two banks in one of said groups then containing valid data is read while data is written to the other bank of the same group in each cycle, valid data being the latest data written, as denoted by what had been stored in said pointer means.
Claim 3
Dependent Claim
59 words
The apparatus of claim 1, wherein the pointer means includes: means for storing, in randomly addressable devices, each having a response time faster than that of the memory banks, pointers to that bank in the first group containing valid data at the first address and to that bank in the second group containing valid data at the second address.
Claim 4
Dependent Claim
89 words
The apparatus of claim 1, wherein the pointer means includes: first means including multiplexer means responsive to the first address for supplying the first address to the one bank in the first group then containing valid data and the third address to the other bank of said first group; and second means including multiplexer means responsive to the second address for supplying the second address to the one bank in the second group then containing valid data and the third address to the other bank in said second group.
Claim 5
Dependent Claim
99 words
The apparatus of claim 1, wherein the pointer means includes: means for storing pointers to the banks containing valid data in the first and second groups; first means, responsive to the stored pointers, for supplying the first address to the one bank then containing valid data in the first group and the third address to the other bank in the first group; and second means, responsive to the stored pointers, for supplying the second address to the one bank then containing valid data in the second group and the third address to the other bank in the second group.
Claim 6
Dependent Claim
106 words
The apparatus of claim 4, wherein the pointer means further includes: means, responsive to the first, second and third addresses within the instruction cycle, for reading from the means for storing pointers a first pointer for the first address and the first group and a second pointer for the second address and the second group to the one bank containing valid data in the first and second groups at the first and second addresses, respectively, and for writing to the means for storing pointers a first pointer and a second pointer to the other bank for the third address in the first and second groups, respectively.
Claim 7
Dependent Claim
193 words
A multiple port memory apparatus, responsive within an instruction cycle to r +w addresses supplied from respective address registers, for supplying data read from r read addresses to output registers and for writing data received from input register means to w write addresses, said writing occurring without requirement of acknowledgement, comprising: r groups each having w+1 memory banks, responsive at a predetermined time in the instruction cycle to the r read addresses and to the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in another of the w+1 banks in another of the r groups; and pointer means for each of the r groups for controlling the w+1 banks of each group so that the one of the w+1 banks in one of said r groups containing valid data is read while data is written to another bank of the same group in each cycle, valid data being the latest data written, as denoted by what had been stored in said pointer means.
Claim 8
Dependent Claim
193 words
A multiple port memory apparatus, responsive within an instruction cycle to r +w addresses supplied from respective address registers, for supplying data read from r read addresses to output registers and for writing data received from input register means to w write addresses, said writing occurring without requirement of acknowledgement, comprising: r groups each having w+1 memory banks, responsive at a predetermined time in the instruction cycle to the r read addresses and to the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in another of the w+1 banks in another of the r groups; and pointer means for each of the r groups for controlling the w+1 banks of each group so that the one of the w+1 banks in one of said r groups containing valid data is read while data is written to another bank of the same group in each cycle, valid data being the latest data written, as denoted by what had been stored in said pointer means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-08-23 | 1992-02-22 | 1992-08-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-08-23 | 1996-02-22 | 1996-08-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-08-23 | 2000-02-22 | 2000-08-23 | $7700.00 | Window Closed / Lapsed |