Patent US4942316A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4942316A Expired / Lapsed US ⏱️ 0.0 years remaining

Cascode logic circuit including a positive level shift at the input of the top logic stage

Assignee: International Business Machines Corp
•
Filing: 1988-11-25
•
Granted: 1990-07-17
•
Expires: 2008-11-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A logic circuit family derived from the conventional 2 level single-ended cascode logic circuit. The basic logic circuit performing a 2--2 OA/AI logic function shown in the attached drawing is given for illustration purposes. It comprises: a logic tree 35 comprised of top and bottom stages 37, 36 dotted at the tree output 38 to perform a determined logic function; the top stage 37 includes a current switch comprised of two input transistors TX34, TX35 connected in a differential amplifier configuration with a reference transistor TX36. The bases of input transistors TX34, TX35 are provided with at least two level shifter devices. Preferably, input level shifter devices are Schottky diodes P31, . . . which move the voltages towards the more positive voltage VPP, to add an AND function on each of these input transistors.

Inventors

  • 👤 Herve Beranger
  • 👤 Armand Brunin
  • 👤 Bruno Caplier
  • 👤 Jean-Paul Rousseau

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 18:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018514; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0866; H03K19/173; H03K19/1733; H03K19/1738; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/289

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 159 words
In a 2N level single-ended cascode logic circuit biased between a first supply voltage and a second supply voltage, wherein N is a positive integer greater than zero, said logic circuit of the type including a logic tree including at least two stacking levels connected in a cascode configuration comprised of top and bottom stages having outputs that are dot-connected to perform predetermined logic function at the tree output; at least one output circuit comprised of an emitter-follower transistor which is driven by the signal at said tree output; wherein each stage includes a current switch each being comprised of at least one input transistor connected in a differential amplifier configuration with a reference transistor; wherein said bottom stage provides a logical OR function; apparatus comprising: at least one input transistor of at least one of said top stages having its input coupled to level shift means for providing a positive voltage shift to an input signal applied thereto.
Claim 2
Dependent Claim 159 words
In a 2N level single-ended cascode logic circuit biased between a first supply voltage and a second supply voltage, wherein N is a positive integer greater than zero, said logic circuit of the type including a logic tree including at least two stacking levels connected in a cascode configuration comprised of top and bottom stages having outputs that are dot-connected to perform predetermined logic function at the tree output; at least one output circuit comprised of an emitter-follower transistor which is driven by the signal at said tree output; wherein each stage includes a current switch each being comprised of at least one input transistor connected in a differential amplifier configuration with a reference transistor; wherein said bottom stage provides a logical OR function; apparatus comprising: at least one input transistor of at least one of said top stages having its input coupled to level shift means for providing a positive voltage shift to an input signal applied thereto.
Claim 3
Dependent Claim 39 words
A 2N level single-ended cascode logic circuit according to claim 1 wherein said level shift means includes means for providing an AND logic function for multiple input signals applied at the input to said at least one input transistor.
Claim 4
Dependent Claim 27 words
A 2N level single-ended cascode logic circuit according to claim 1 wherein said level shift means are selected from the group consisting of PN or Schottky diodes.
Claim 5
Dependent Claim 30 words
A 2N level single-ended cascode logic circuit according to claim 1 wherein said level shift means includes Schottky Barrier Diodes whose anodes are connected together and to a load resistor.
Claim 6
Dependent Claim 50 words
A 2N level single-ended cascode logic circuit according to claim 1 wherein said output circuit includes a single output available on the emitter of said emitter follower transistor, said single output capable of driving both the top and bottom stage inputs of another 2N level single ended cascode logic circuit.
Claim 7
Dependent Claim 27 words
A 2N level single-ended cascode logic circuit according to claim 1 wherein the input and reference transistors of the top stage are connected to purely resistive loads.
Claim 8
Dependent Claim 25 words
A 2N level single-ended cascode logic circuit according to claim 1 wherein said predetermined logic function is either an OR or an AND logic function.

References Cited (Backward Citations)

US957007A Cited
UST957007I4 Cited
US4518876A Cited
US4547881A Cited
US4533842A Cited
US4580066A Cited
US4647799A Cited
EP0167339A2 Cited
EP0176909A1 Cited
US4631427A Cited
US4670673A Cited
US4845387A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-07-16 1994-01-15 1994-07-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-07-16 1998-01-15 1998-07-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-07-16 2002-01-15 2002-07-17 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag