US4631427A
Expired / Lapsed
US
⏱️ 0.0 years remaining
ECL gate circuit having internally generated reference voltages
Assignee: Advanced Micro Devices Inc
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Filing: 1984-11-19
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Granted: 1986-12-23
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Expires: 2004-11-19
Abstract
Abstract An improved ECL circuit in which reference voltages have been eliminated is provided. The base of the reference switching transistor which is usually connected to a reference voltage is instead connected to the emitter of an emitter follower transistor coupled to the input switching transistor. The need for a reference voltage is thus eliminated because the emitter of such emitter follower transistor, and thus the base of the reference switching transistor, will be at the opposite level of the input to the base of the input switching transistor.
Inventors
- 👤 Nikhil C. Mazumder
- 👤 David H. B. Yee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:31
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03K19/003; H03K19/00346; H03K19/00353; H03K19/0866
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
276 words
An emitter coupled logic (ECL) gate circuit having internally generated reference voltages in which externally generated reference voltages are eliminated, said circuit comprising: a first level of switching transistors being formed of a first input transistor and a first reference transistor, said first input transistor and said first reference transistor having their emitters coupled to a current source, said first input transistor having its base coupled to a first level input terminal, said first reference transistor having a base and collector; first and second emitter follower transistors, said first emitter follower transistor being coupled to said first reference transistor, said second emitter follower transistor being coupled to said first input transistor, said second emitter follower transistor having its emitter coupled to the base of said first reference transistor; at least a second level of switching transistors being formed of a second input transistor and a second reference transistor, said second level of switching transistors coupling said first level of switching transistors to said current source, said second input transistor and said second reference transistor having their emitters coupled to said current source, said second input transistor having its base coupled to a second level input terminal and its collector coupled to the emitters of said first level of switching transistors, said second reference transistor having a base and collector, said second reference transistor having its collector coupled to the collector of said first reference transistor; and means, coupling the base of said first reference transistor to the base of said second reference transistor, for producing a second level reference voltage substantially proportional to a first level reference voltage at the base of said first reference transistor.
Claim 2
Dependent Claim
276 words
An emitter coupled logic (ECL) gate circuit having internally generated reference voltages in which externally generated reference voltages are eliminated, said circuit comprising: a first level of switching transistors being formed of a first input transistor and a first reference transistor, said first input transistor and said first reference transistor having their emitters coupled to a current source, said first input transistor having its base coupled to a first level input terminal, said first reference transistor having a base and collector; first and second emitter follower transistors, said first emitter follower transistor being coupled to said first reference transistor, said second emitter follower transistor being coupled to said first input transistor, said second emitter follower transistor having its emitter coupled to the base of said first reference transistor; at least a second level of switching transistors being formed of a second input transistor and a second reference transistor, said second level of switching transistors coupling said first level of switching transistors to said current source, said second input transistor and said second reference transistor having their emitters coupled to said current source, said second input transistor having its base coupled to a second level input terminal and its collector coupled to the emitters of said first level of switching transistors, said second reference transistor having a base and collector, said second reference transistor having its collector coupled to the collector of said first reference transistor; and means, coupling the base of said first reference transistor to the base of said second reference transistor, for producing a second level reference voltage substantially proportional to a first level reference voltage at the base of said first reference transistor.
Claim 3
Dependent Claim
32 words
The ECL circuit of claim 1 wherein said means for producing the second level reference voltage is a first diode with its anode coupled to the base of said first reference transistor.
Claim 4
Dependent Claim
38 words
The ECL circuit of claim 2 further comprising: a second diode having its anode coupled to the emitter of said first emitter follower transistor to provide a second level non-inverting outupt at the cathode of said second diode.
Claim 5
Dependent Claim
151 words
The ECL circuit of claim 3 further comprising: a third level of switching transistors being formed of a third input transistor and a third reference transistor, said third level of switching transistors coupling said second level of switching transistors to said current source, said third input transistor and said third reference transistor having their emitters coupled to said current source, said third input transistor having its base coupled to a third level input terminal and its collector coupled to the emitters of said second level of switching transistors, said third reference transistor having a base and a collector, said third reference transistor having its collector coupled to the collector of said second reference transistor; and a third diode coupling the base of said second reference transistor to the base of said third reference transistor with the anode of said third diode being coupled to the base of said second reference transistor.
Claim 6
Dependent Claim
36 words
The ECL circuit of claim 4 further comprising: a fourth diode having its anode coupled to the cathode of said second diode to provide a third level non-inverting output at the cathode of said fourth diode.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-12-22 | 1990-06-23 | 1990-12-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-12-22 | 1994-06-23 | 1994-12-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-12-22 | 1998-06-23 | 1998-12-23 | $7700.00 | Window Closed / Lapsed |