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US4939720A
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Unit for switching data transmitted by asynchronous time-division multiplexing
Assignee: Alcatel CIT SA
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Filing: 1988-11-28
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Granted: 1990-07-03
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Expires: 2008-11-28
Abstract
Abstract The invention concerns a unit for switching data transmitted by asynchronous time-division multiplexing comprising receive circuits (CRl/i) supplying cells received via input links, transmit circuits (CTl/j) transmitting retransmitted cells on output links, a buffer memory (MT) storing the received cells and delivering the cells to be retransmitted and a buffer memory addressing device (SMT) including a write address source (SAE) and a read address source (fsl/j). The switching unit further comprises a write disabling circuit (pi) conditioned by a signal (adl) derived from the content of at least one received cell or a signal (tle) derived from the absence of any received cell and supplying a disabling signal (spi) and the address source includes a disabling device (pac, pal) influenced by the disabling signal (spi) so that no memory location is then occupied in the buffer memory (MT).
Inventors
- 👤 Raymond Bakka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:33
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/108; H04L49/40; H04L49/405; H04L2012/5672
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
173 words
A unit for switching data transmitted by asynchronous time-division multiplexing comprising: receive circuits each associated with an input link and supplying cells received via said input link; transmit circuits each associated with an output link and transmitting retransmitted cells on said output link; a buffer memory storing received cells supplied by the receive circuit and delivering cells to be retransmitted to the transmit circuit; and a buffer memory addressing device for addressing said buffer memory comprising a write address source and a read address source; characterized in that the switching unit further comprises a write disabling circuit (pi) conditioned by a signal (adl) derived from the content of at least one of said received cells or a signal (tle) derived from the absence of any of said received cells and supplying a disabling signal (spi) to said buffer memory addressing device and in that the write address source comprises a disabling device (pac, pal) influenced by said disabling signal (spi) such that no memory location is then written in the buffer memory (MT).
Claim 2
Dependent Claim
173 words
A unit for switching data transmitted by asynchronous time-division multiplexing comprising: receive circuits each associated with an input link and supplying cells received via said input link; transmit circuits each associated with an output link and transmitting retransmitted cells on said output link; a buffer memory storing received cells supplied by the receive circuit and delivering cells to be retransmitted to the transmit circuit; and a buffer memory addressing device for addressing said buffer memory comprising a write address source and a read address source; characterized in that the switching unit further comprises a write disabling circuit (pi) conditioned by a signal (adl) derived from the content of at least one of said received cells or a signal (tle) derived from the absence of any of said received cells and supplying a disabling signal (spi) to said buffer memory addressing device and in that the write address source comprises a disabling device (pac, pal) influenced by said disabling signal (spi) such that no memory location is then written in the buffer memory (MT).
Claim 3
Dependent Claim
75 words
A switching unit according to claim 1, characterized in that said write address source comprises an address counter (cae) provided with an indexing input (ei) receiving an indexing signal causing the counter to advance by one step following writing of a cell into the buffer memory and in that said disabling signal (spi) is operative on said indexing input via means (pac) of said disabling device enabling transmission of said indexing signal to be prevented.
Claim 4
Dependent Claim
61 words
A switching unit according to claim 1 characterized in that said write address source further comprises a released address memory (fal) receiving the addresses of locations of the buffer memory released by cell already retransmitted and supplying these addresses in place of an address counter (cae) of said write address source as soon as it contains at least one of them.
Claim 5
Dependent Claim
56 words
A switching unit according to claim 2 characterized in that said write address source further comprises a released address memory (fal) receiving the addresses of locations of the buffer memory released by cells already retransmitted and supplying these addressee in place of the address counter (cae) as soon as it contains at least one of them.
Claim 6
Dependent Claim
33 words
A switching unit according to claim 3 or 4 further comprising means (pal) on which said disabling signal (spi) is operative to prevent reading of an address in said released address memory (fal).
Claim 7
Dependent Claim
19 words
A switching unit according to claim 5 characterized in that the released address memory (fal) is an FIFO memory.
Claim 8
Dependent Claim
46 words
A switching unit according to claim 1 characterized in that the receive circuit of an input link comprises a cell absence identification circuit (bca, pcd, psv) which supplies a signal (tle) which is transmitted to said write disabling circuit (pi) to produce said disabling signal (spi).
Claim 9
Dependent Claim
76 words
A switching unit according to claim 1 characterized in that an address decoding circuit (cda) is provided to receive an address part (AD1) of a label field (EE) of a cell presented to the buffer memory, an ouytput (ad1) of this address decoding circuit (cda) supplying a signal in the presence of a cell that is not to be retransmitted, which signal is transmitted to said write disabling circuit (pi) to produce said disabling signal (spi).
Claim 10
Dependent Claim
65 words
A switching unit according to claim 1 in which each of the cells to be retransmitted contains several addressed (AD1, AD2, . . . ) that are to be used in the switching units passed through in succession, characterized in that an address decoding circuit (cda) decodes a first address of the received cell and supplies a decoded output address to said read address source.
Claim 11
Dependent Claim
45 words
A switching unit according to claim 9 characterized in that a cell is transferred from an input link to an output link via an address permutation circuit (CPA) which moves a second address contained in a cell to be retransmitted into a first address position.
Claim 12
Dependent Claim
46 words
A switching unit according to claim 1 characterized in that each of the cells contains a virtual circuit indication (Cv) and further comprising a virtual circuit memory (mcv) for receiving said virtual circuit indication (Cv) and supplying a decoded output address to said read address source.
Claim 13
Dependent Claim
29 words
A switching unit according to claim 11 characterized in that siad virtual circuit memory (mcv) supplies a virtual circuit indication (Cv) which replaces that which the received cell contained.
Claim 14
Dependent Claim
170 words
A switching unit according to any one of claims 3, 4, 7, 8, 9 or 11 wherein provision is made for retransmitting a received cell on more than one output link (broadcasting), characterized in that it further comprises a broadcast memory (MD) containing a memory location for each memory location of the buffer memory (MT) adapted to store a bit corresponding to each output link, writing means (mxd, pei, mxa) whereby this bit may be assigned a specific value when a cell stored in the memory location of the buffer memory (MT) is to be retransmitted on the link to which it corresponds, erasing means (mdf) whereby this bit can be assigned the opposite value when the cell in question has been retransmitted on the link to which it corresponds, and cell release means (rdz) enabling writing of the address of the cell in question into the released address memory (fal) only when all the bits of the location in question of the broadcast memory (MD) have said opposite values.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |