US4788679A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Packet switch with variable data transfer rate links
Assignee: NTT Inc
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Filing: 1987-08-10
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Granted: 1988-11-29
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Expires: 2007-08-10
Abstract
Abstract A packet switch has pluralities of incoming and outgoing trunks, a data memory accessible from them in common, and FIFO memories each provided in each of input and output circuits. Data from the incoming trunks is written into and read out from the buffer memory for transfer to the outgoing trunks, on a time-shared basis, to perform packet switching between trunks of different data transfer rates. Furthermore, the packet switch has an arbiter for detecting process requests from the input circuits and an arbiter for detecting process requests from the output circuits, so that priority control is effected for servicing the requests. As a result, dynamic allocation of access to the buffer memory to the input and output circuits is permitted.
Inventors
- 👤 Hideki Kataoka
- 👤 Tatsuro Takahashi
- 👤 Shiro Kikuchi
- 👤 Naoaki Yamanaka
- 👤 Hajime Sakakibara
- 👤 Miki Hirano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:18
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/10; H04L49/103; H04L49/15; H04L49/1515; H04L49/30
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
376 words
A packet switch with variable data transfer rate links, which forms a packet switching network of a packet switching system, comprising: a multi-stage structure including a plurality of unit packet switches, each of said unit packet switches including: connections for a plurality of incoming trunks; a plurality of input circuits connected to said connections for the plurality of incoming trunks, respectively, and each having a FIFO memory; connections for a plurality of outgoing trunks; a plurality of output circuits connected to said connections for the plurality of outgoing trunks, respectively, and each having a FIFO memory; a buffer memory which is used in common for the incoming trunks and the outgoing trunks, by writing data received from the incoming trunks and reading it out for transfer to the outgoing trunks, the FIFO memory of each of the input circuits for temporarily storing the received data from the corresponding incoming trunk, the FIFO memory of each of the output circuits for temporarily storing the data to be sent to the corresponding outgoing trunk; first signal lines, respectively connected to said input circuits, for providing information indicating the arrival of data at the corresponding input circuit from the incoming trunk connected thereto; a first arbiter, connected to said first signal lines, for detecting data-process requests from said input circuits on the basis of the information provided on said first signal lines and for effecting priority control for servicing the requests; second signal lines, respectively connected to said output circuits, for providing information indicating whether or not data transfer to the corresponding output circuit is possible; and a second arbiter connected to said second signal lines, for detecting data-process requests from said output circuits on the basis of the information provided on said second signal lines and for effecting priority control for servicing the requests; links interconnecting the respective stages of the unit packet switches, for performing asynchronous packet data transfer by handshaking; and a control circuit for controlling the data transfer by handshaking while dynamically changing the capacity of each of said links within a range in which the sum of data transfer rates of said links accommodated in each unit packet switch is smaller than the operational speed of said buffer memory in said unit packet switch.
Claim 2
Dependent Claim
376 words
A packet switch with variable data transfer rate links, which forms a packet switching network of a packet switching system, comprising: a multi-stage structure including a plurality of unit packet switches, each of said unit packet switches including: connections for a plurality of incoming trunks; a plurality of input circuits connected to said connections for the plurality of incoming trunks, respectively, and each having a FIFO memory; connections for a plurality of outgoing trunks; a plurality of output circuits connected to said connections for the plurality of outgoing trunks, respectively, and each having a FIFO memory; a buffer memory which is used in common for the incoming trunks and the outgoing trunks, by writing data received from the incoming trunks and reading it out for transfer to the outgoing trunks, the FIFO memory of each of the input circuits for temporarily storing the received data from the corresponding incoming trunk, the FIFO memory of each of the output circuits for temporarily storing the data to be sent to the corresponding outgoing trunk; first signal lines, respectively connected to said input circuits, for providing information indicating the arrival of data at the corresponding input circuit from the incoming trunk connected thereto; a first arbiter, connected to said first signal lines, for detecting data-process requests from said input circuits on the basis of the information provided on said first signal lines and for effecting priority control for servicing the requests; second signal lines, respectively connected to said output circuits, for providing information indicating whether or not data transfer to the corresponding output circuit is possible; and a second arbiter connected to said second signal lines, for detecting data-process requests from said output circuits on the basis of the information provided on said second signal lines and for effecting priority control for servicing the requests; links interconnecting the respective stages of the unit packet switches, for performing asynchronous packet data transfer by handshaking; and a control circuit for controlling the data transfer by handshaking while dynamically changing the capacity of each of said links within a range in which the sum of data transfer rates of said links accommodated in each unit packet switch is smaller than the operational speed of said buffer memory in said unit packet switch.
Claim 3
Dependent Claim
33 words
A packet switch according to claim 1, wherein each of said output circuits includes a parallel to serial transform circuit for transforming parallel data read out from said buffer memory into serial data.
Claim 4
Dependent Claim
32 words
A packet switch according to claim 2, wherein each of said input circuits comprises a serial to parallel transform circuit for transforming serial data received from the corresponding link into parallel data.
Claim 5
Dependent Claim
170 words
A packet switch coupled to incoming trunks and outgoing trunks, comprising: a multi-stage structure including a plurality of unit packet switches, each of which includes: a plurality of input circuits coupled to the plurality of incoming trunks, respectively; a plurality of output circuits coupled to the plurality of outgoing trunks, respectively; a buffer memory coupled to said input circuits and to said output circuits, said buffer memory being used in common by the incoming trunks and outgoing trunks by writing data received from the incoming trunks and reading it out for transfer to the outgoing trunks; links interconnecting the respective stages of the unit packet switches, for performing asynchronous packet data transfer by handshaking; and a control circuit for controlling the data transfer by handshaking while dynamically changing the capacity of each of said links within a range in which the sum of data transfer rates of said links accommodated in each unit packet switch is smaller than the operational speed of said buffer memory in said unit packet switch.
Claim 6
Dependent Claim
170 words
A packet switch coupled to incoming trunks and outgoing trunks, comprising: a multi-stage structure including a plurality of unit packet switches, each of which includes: a plurality of input circuits coupled to the plurality of incoming trunks, respectively; a plurality of output circuits coupled to the plurality of outgoing trunks, respectively; a buffer memory coupled to said input circuits and to said output circuits, said buffer memory being used in common by the incoming trunks and outgoing trunks by writing data received from the incoming trunks and reading it out for transfer to the outgoing trunks; links interconnecting the respective stages of the unit packet switches, for performing asynchronous packet data transfer by handshaking; and a control circuit for controlling the data transfer by handshaking while dynamically changing the capacity of each of said links within a range in which the sum of data transfer rates of said links accommodated in each unit packet switch is smaller than the operational speed of said buffer memory in said unit packet switch.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-29 | 1992-05-30 | 1992-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-29 | 1996-05-30 | 1996-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-29 | 2000-05-30 | 2000-11-29 | $7700.00 | Window Closed / Lapsed |