Process for the production of a MIS transistor with a raised substrate/gate dielectric interface end

Claim 1

A process for the production of a MIS transistor, comprising the following successive steps: forming on the surface of a semiconductor substrate having a given doping type a first electrically insulating layer which surrounds a surface zone of the substrate; forming a second layer on the first insulating layer and on said zone; exposing part of said zone by eliminating a fragment of the second layer, said fragment extending about said part, which thus constitutes the bottom of a hole made in the second layer, and above a part of the first insulating layer; forming a recess having at least one rising wall in the bottom of said hole; forming a third electrically insulating layer on the surface of said part of said zone; forming an electrically conductive layer on the substrate; eliminating said electrically conductive layer except in a zone corresponding to said fragment, so as to obtain a transistor gate by etching back of the electrically conductive layer; eliminating the remainder of the second layer; and forming on either side of the gate source and drain zones of the transistor in such a way that said source and drain zones respectively have portions extending beneath the interface which the third layer has with the substrate, the source and drain zones having a doped type opposite to that of the substrate, the drain zone being located on the side of said rising wall of the recess, wherein, before or after forming the third insulating layer, ions giving rise to a doping of the same type as that of the substrate are locally implanted in the substrate in a zone thereof which corresponds to a transistor channel, under the third insulating layer.