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US4939071A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming low resistance, sub-micrometer semiconductor gate structures
Assignee: Samsung Semiconductor Inc
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Filing: 1984-03-06
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Granted: 1990-07-03
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Expires: 2004-03-06
Abstract
Abstract A process for forming a T or Y gate structures on the surface of semiconductor device substrates is disclosed wherein the gate length is extremely small, and low resistance along the gate width using light field photolithographic processing techniques, and a positive photo-resist, which allows definition of areas of smaller dimension than conventional dark field photolithographic techniques.
Inventors
- 👤 Joseph S. Barrera
- 👤 Charles T. Strouth
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:28
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/20; G03F7/2002; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/947; Y10S438/948
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
127 words
A method of providing on a support of a substrate a covering layer having at least one sub-micron-size recess therein, comprising the steps of: covering at least a section of the support surface that includes the desired location of the recess with a photoresist layer; masking an area of the photoresist layer that covers said location, such masked area having a size exceeding the desired size of the recess; subjecting the photoresist layer to overexposure with an attendant reduction in the size of said masked area down to said desired size of the recess; removing the photoresist layer from a region of the support surface surrounding the reduced-size area; applying the covering layer at least to said region; and clearing said reduced-size area to provide the recess.
Claim 2
Independent Claim
127 words
A method of providing on a support of a substrate a covering layer having at least one sub-micron-size recess therein, comprising the steps of: covering at least a section of the support surface that includes the desired location of the recess with a photoresist layer; masking an area of the photoresist layer that covers said location, such masked area having a size exceeding the desired size of the recess; subjecting the photoresist layer to overexposure with an attendant reduction in the size of said masked area down to said desired size of the recess; removing the photoresist layer from a region of the support surface surrounding the reduced-size area; applying the covering layer at least to said region; and clearing said reduced-size area to provide the recess.
Claim 3
Independent Claim
134 words
A method of fabricating a sub-micron-size gate on a support surface of a semiconductor substrate, comprising the steps of: covering at least a section of the support surface that includes the desired location of the gate with a photoresist layer; masking an area of the photoresist layer that covers said location, such masked area having a size exceeding the desired size of the gate; subjecting the photoresist layer to overexposure with an attendant reduction in the size of said masked area down to said desired size of the gate; removing the photoresist layer from a region of the support surface surrounding the reduced-size area; providing a protective coating at least on said region; clearing said reduced-size area to provide a recess in said protective coating; and depositing gate material at least in said recess.
Claim 4
Independent Claim
134 words
A method of fabricating a sub-micron-size gate on a support surface of a semiconductor substrate, comprising the steps of: covering at least a section of the support surface that includes the desired location of the gate with a photoresist layer; masking an area of the photoresist layer that covers said location, such masked area having a size exceeding the desired size of the gate; subjecting the photoresist layer to overexposure with an attendant reduction in the size of said masked area down to said desired size of the gate; removing the photoresist layer from a region of the support surface surrounding the reduced-size area; providing a protective coating at least on said region; clearing said reduced-size area to provide a recess in said protective coating; and depositing gate material at least in said recess.
Claim 5
Dependent Claim
30 words
The method as defined in claim 2, wherein said providing step includes depositing a layer of a silicon compound selected from the group consisting of silicon dioxide and silicon nitride.
Claim 6
Dependent Claim
22 words
The method as defined in claim 2, wherein said clearing step includes a lift-off of the photoresist material to provide said recess.
Claim 7
Dependent Claim
235 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a first layer of positive photo-resist material on the surface of said substrate; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said photo-resist and thereafter irradiating the portions of said first layer of photo-resist not shielded from irradiation by said mask; removing said irradiated portions of said first layer of photo-resist; forming a dielectric layer on the surface of said substrate and remaining photo-resist material portion; removing said remaining photo-resist material and the portion of said dielectric layer overlaying said remaining photo-resist portion, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a first metal layer over said dielectric layer and in contact with said exposed portion of said substrate surface; forming a second photo-resist layer over said first metal layer and photolithographically defining an area in said second photo-resist layer overlaying an overhanging said portion of said first metal layer in contact with said substrate; removing said defined area thereby forming an opening in said second photo-resist layer; forming a second metal layer in said opening; and removing all of said second photo-resist layer and all of said first metal layer except that portion directly underlying said second metal layer.
Claim 8
Dependent Claim
235 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a first layer of positive photo-resist material on the surface of said substrate; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said photo-resist and thereafter irradiating the portions of said first layer of photo-resist not shielded from irradiation by said mask; removing said irradiated portions of said first layer of photo-resist; forming a dielectric layer on the surface of said substrate and remaining photo-resist material portion; removing said remaining photo-resist material and the portion of said dielectric layer overlaying said remaining photo-resist portion, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a first metal layer over said dielectric layer and in contact with said exposed portion of said substrate surface; forming a second photo-resist layer over said first metal layer and photolithographically defining an area in said second photo-resist layer overlaying an overhanging said portion of said first metal layer in contact with said substrate; removing said defined area thereby forming an opening in said second photo-resist layer; forming a second metal layer in said opening; and removing all of said second photo-resist layer and all of said first metal layer except that portion directly underlying said second metal layer.
Claim 9
Dependent Claim
303 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a layer of dielectric matrerial on the surface of said substrate; forming a first layer of positive photo-resist material on said dielectric layer; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said first photo-resist layer and thereafter irradiating the portions of said first photo-resist layer not shielded from irradiation by said mask; removing said irradiated portions of said first photo-resist layer; forming a thin metal layer over said dielectric layer and the remaining portion of said first photo-resist layer; removing said remaining portion of said first photo-resist layer and the portion of said thin metal layer overlaying said remaining portion of said first photo-resist layer thereby creating an opening in said thin metal layer to said dielectric layer over the portion of said substrate surface to be contacted by said gate structure; removing the portion of said dielectric layer directly underneath said opening in said thin metal layer, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a second metal layer over said thin metal layer and in contact with said exposed portion of said substrate surface; forming a second photo-resist layer over said second metal layer and photolithographically defining an opening in said second photo-resist layer overlaying and overhanging said portion of said second metal layer in contact with said substrate; removing said defined area, thereby forming an opening in said second photo-resist layer; forming a third metal layer in said opening; and removing all of said second photo-resist layer, thin metal layer and all of said second metal layer except that portion underlying said third metal layer.
Claim 10
Dependent Claim
303 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a layer of dielectric matrerial on the surface of said substrate; forming a first layer of positive photo-resist material on said dielectric layer; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said first photo-resist layer and thereafter irradiating the portions of said first photo-resist layer not shielded from irradiation by said mask; removing said irradiated portions of said first photo-resist layer; forming a thin metal layer over said dielectric layer and the remaining portion of said first photo-resist layer; removing said remaining portion of said first photo-resist layer and the portion of said thin metal layer overlaying said remaining portion of said first photo-resist layer thereby creating an opening in said thin metal layer to said dielectric layer over the portion of said substrate surface to be contacted by said gate structure; removing the portion of said dielectric layer directly underneath said opening in said thin metal layer, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a second metal layer over said thin metal layer and in contact with said exposed portion of said substrate surface; forming a second photo-resist layer over said second metal layer and photolithographically defining an opening in said second photo-resist layer overlaying and overhanging said portion of said second metal layer in contact with said substrate; removing said defined area, thereby forming an opening in said second photo-resist layer; forming a third metal layer in said opening; and removing all of said second photo-resist layer, thin metal layer and all of said second metal layer except that portion underlying said third metal layer.
Claim 11
Dependent Claim
199 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a first layer of positive photo-resist material on the surface of said substrate; providing a first light field mask defining the portion of said substrate surface to be contacted by said gate structure on said photo-resist and thereafter irradiating the portions of said first layer of photo-resist not shielded from irradiation by said mask; removing said irradiated portions of said first layer of photo-resist; forming a dielectric layer on the surface of said substrate and remaining photo-resist material portion; removing said remaining photo-resist material and the portion of said dielectric layer overlaying said remaining photo-resist portion, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a metal layer over said dielectric layer and in contact with said exposed porton of said substrate surface; forming a second mask over said metal layer defining an area on said metal layer overlaying and overhanging said portion of said first metal layer in contact with said substrate; removing said metal layer except in said defined area; and removing said second mask.
Claim 12
Dependent Claim
199 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a first layer of positive photo-resist material on the surface of said substrate; providing a first light field mask defining the portion of said substrate surface to be contacted by said gate structure on said photo-resist and thereafter irradiating the portions of said first layer of photo-resist not shielded from irradiation by said mask; removing said irradiated portions of said first layer of photo-resist; forming a dielectric layer on the surface of said substrate and remaining photo-resist material portion; removing said remaining photo-resist material and the portion of said dielectric layer overlaying said remaining photo-resist portion, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a metal layer over said dielectric layer and in contact with said exposed porton of said substrate surface; forming a second mask over said metal layer defining an area on said metal layer overlaying and overhanging said portion of said first metal layer in contact with said substrate; removing said metal layer except in said defined area; and removing said second mask.
Claim 13
Dependent Claim
270 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a layer of dielectric material on the surface of said substrate; forming a first layer of positive photo-resist material on said dielectric layer; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said first photo-resist layer and thereafter irradiating the portions of said first photo-resist layer not shielded from irradiation by said mask; removing said irradiated portions of said first photo-resist layer; forming a thin metal layer over said dielectric layer and the remaining portion of said first photo-resist layer; removing said remaining portion of said first photo-resist layer and the portion of said thin metal layer overlaying said remaining portion of said first photo-resist layer thereby creating an opening in said thin metal layer to said dielectric layer over the portion of said substrate surface to be contacted by said gate structure; removing the portion of said dielectric layer directly underneath said opening in said thin metal layer, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a second metal layer over said thin metal layer and in contact with said exposed portion of said substrate surface; forming a second mask over said second metal layer defining an area on said second metal layer overlaying and overhanging said portion of said second metal layer in contact with said substrate; removing said thin and second metal layer except in said defined area; and removing said second mask.
Claim 14
Dependent Claim
270 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a layer of dielectric material on the surface of said substrate; forming a first layer of positive photo-resist material on said dielectric layer; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said first photo-resist layer and thereafter irradiating the portions of said first photo-resist layer not shielded from irradiation by said mask; removing said irradiated portions of said first photo-resist layer; forming a thin metal layer over said dielectric layer and the remaining portion of said first photo-resist layer; removing said remaining portion of said first photo-resist layer and the portion of said thin metal layer overlaying said remaining portion of said first photo-resist layer thereby creating an opening in said thin metal layer to said dielectric layer over the portion of said substrate surface to be contacted by said gate structure; removing the portion of said dielectric layer directly underneath said opening in said thin metal layer, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; forming a second metal layer over said thin metal layer and in contact with said exposed portion of said substrate surface; forming a second mask over said second metal layer defining an area on said second metal layer overlaying and overhanging said portion of said second metal layer in contact with said substrate; removing said thin and second metal layer except in said defined area; and removing said second mask.
Claim 15
Dependent Claim
271 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a layer of dielectric material on the surface of said substrate; forming a first layer of positive photo-resist material on said dielectric layer; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said first photo-resist layer and thereafter irradiating the portions of said first photo-resist layer not shielded from irradiation by said mask; removing said irradiated portions of said first photo-resist layer; forming a thin metal layer over said dielectric layer and the remaining portion of said first photo-resist layer; removing said remaining portion of said first photo-resist layer and the portion of said thin metal layer overlaying said remaining portion of said first photo-resist layer thereby creating an opening in said thin metal layer to said dielectric layer over a portion of said substrate surface to be contacted by said gate structure; removing the portion of said dielectric layer directly underneath said opening in said thin metal layer, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; removing said thin metal layer; forming a second metal layer over said dielectric layer and in contact with said exposed portion of said substrate surface; forming a second mask over said second metal layer defining an area on said second metal layer overlaying and overhanging said portion of said second metal layer in contact with said substrate; removing said second metal layer except in said defined area; and removing said mask.
Claim 16
Dependent Claim
271 words
A process for formation of gate structures of extremely small length on a surface of a semiconductor substrate, comprising: forming a layer of dielectric material on the surface of said substrate; forming a first layer of positive photo-resist material on said dielectric layer; providing a light field mask defining the portion of said substrate surface to be contacted by said gate structure on said first photo-resist layer and thereafter irradiating the portions of said first photo-resist layer not shielded from irradiation by said mask; removing said irradiated portions of said first photo-resist layer; forming a thin metal layer over said dielectric layer and the remaining portion of said first photo-resist layer; removing said remaining portion of said first photo-resist layer and the portion of said thin metal layer overlaying said remaining portion of said first photo-resist layer thereby creating an opening in said thin metal layer to said dielectric layer over a portion of said substrate surface to be contacted by said gate structure; removing the portion of said dielectric layer directly underneath said opening in said thin metal layer, thereby exposing the portion of said substrate surface of less than one micron to be contacted by said gate structure; removing said thin metal layer; forming a second metal layer over said dielectric layer and in contact with said exposed portion of said substrate surface; forming a second mask over said second metal layer defining an area on said second metal layer overlaying and overhanging said portion of said second metal layer in contact with said substrate; removing said second metal layer except in said defined area; and removing said mask.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-07-02 | 1994-01-01 | 1994-07-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-07-02 | 1998-01-01 | 1998-07-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-07-02 | 2002-01-01 | 2002-07-03 | $7700.00 | Window Closed / Lapsed |