Patent US4935719A successfully refreshed from Google Patents.
US4935719A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Comparator circuitry
Assignee: STMicroelectronics lnc USA
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Filing: 1989-03-31
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Granted: 1990-06-19
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Expires: 2009-03-31
Abstract
Abstract Two sets of binary data of N bits in length are compared by first forming the exclusive OR function of each of the corresponding bits of the two data sets. The output of each of the exclusive OR gates controls two sets of transmission gates in each of N comparator circuits which are combined in series. If an individual pair of bits are the same, then the comparator circuit transfers the data from its compare input to its compare output, and if the individual bits are different, the respective compare circuit transfers the data from the respective bit on one of the buses to the compare output of the circuit. The compare input of the first compare circuit is connected to ground and the compare input of the rest of the comparator circuits is connected to the compare output of the previous circuit and the compare output of the Nth compare circuit forms a signal indicative of whether the data on the first bus is greater than the data on the second bus.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:59
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F7/026
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
390 words
Circuitry for detecting if the difference between two numbers represented as logic levels on first and second data busses is less than or greater than a preset value comprising: (a) a subtractor chain having a plurality of subtractor circuits in series with a first subtractor circuit at one end of said subtractor chain and an Nth subtractor circuit at the other end of said subtractor chain, each of said subtractor circuits comprising: (i) a difference output terminal and a borrow output terminal; (ii) first and second input terminals coupled to one signal line each of said first and second data busses respectively and a borrow input terminal, said borrow input terminal coupled to a first reference voltage in said first subtractor circuit and the borrow input terminals of the rest of said subtractor circuits being coupled to the borrow output terminal of the preceding subtractor circuit in said subtractor chain; (iii) circuitry which determines the arithmetic difference between the number on said first bus and the number on said second bus combined with said borrow input signal and which produces said difference output signal and said borrow output signal; (b) a comparator chain having a plurality of comparator circuits, corresponding to said subtractor circuits, in series with a first comparator circuit at one end of said comparator chain and an Nth comparator circuit at the other end of said comparator chain, each of said comparator circuits comprising: (i) an output terminal; (ii) a preset bit input coupled to one bit of said preset value, a difference input coupled to the difference output of a corresponding subtractor circuit of said subtractor chain, and a compare input, said compare input coupled to a second reference voltage in said first comparator circuit, and the compare inputs of the remainder of said comparator circuits being coupled to the output terminal of the previous comparator circuit; (iii) switch circuitry which couples said preset value input to said output terminal when said difference input is at a first logic state and which couples said compare input to said output terminal when said difference input is at a second logic state; and (iv) wherein said output terminal of said Nth comparator circuit forms an output indicative of whether the difference between said two numbers on said first and second data busses is greater than said preset value.
Claim 2
Dependent Claim
390 words
Circuitry for detecting if the difference between two numbers represented as logic levels on first and second data busses is less than or greater than a preset value comprising: (a) a subtractor chain having a plurality of subtractor circuits in series with a first subtractor circuit at one end of said subtractor chain and an Nth subtractor circuit at the other end of said subtractor chain, each of said subtractor circuits comprising: (i) a difference output terminal and a borrow output terminal; (ii) first and second input terminals coupled to one signal line each of said first and second data busses respectively and a borrow input terminal, said borrow input terminal coupled to a first reference voltage in said first subtractor circuit and the borrow input terminals of the rest of said subtractor circuits being coupled to the borrow output terminal of the preceding subtractor circuit in said subtractor chain; (iii) circuitry which determines the arithmetic difference between the number on said first bus and the number on said second bus combined with said borrow input signal and which produces said difference output signal and said borrow output signal; (b) a comparator chain having a plurality of comparator circuits, corresponding to said subtractor circuits, in series with a first comparator circuit at one end of said comparator chain and an Nth comparator circuit at the other end of said comparator chain, each of said comparator circuits comprising: (i) an output terminal; (ii) a preset bit input coupled to one bit of said preset value, a difference input coupled to the difference output of a corresponding subtractor circuit of said subtractor chain, and a compare input, said compare input coupled to a second reference voltage in said first comparator circuit, and the compare inputs of the remainder of said comparator circuits being coupled to the output terminal of the previous comparator circuit; (iii) switch circuitry which couples said preset value input to said output terminal when said difference input is at a first logic state and which couples said compare input to said output terminal when said difference input is at a second logic state; and (iv) wherein said output terminal of said Nth comparator circuit forms an output indicative of whether the difference between said two numbers on said first and second data busses is greater than said preset value.
Claim 3
Dependent Claim
18 words
Circuitry set forth in claim 1 wherein said first and second reference voltages are the same voltage potential.
Claim 4
Dependent Claim
62 words
Circuitry set forth in claim 1 wherein said borrow output terminal of at least one of said subtractor circuits is coupled to said borrow input terminal of the next succeeding subtractor circuit through an inverter, and said output terminal of at least one of said comparator circuits is coupled to said compare input of the next succeeding comparator circuit through an inverter.
Claim 5
Dependent Claim
34 words
Circuitry as set forth in claim 1 wherein said difference output terminal of at least one of said subtractor circuits is inverted when coupled to said difference input terminal of the corresponding comparator circuit.
Claim 6
Dependent Claim
251 words
Circuitry for detecting if the number on a first data set, A, is greater than the number on a second data set, B, both of N bits in length, comprising: (a) an N plurality of exclusive OR gates, each of said exclusive OR gates having as inputs a data bit from said A data set and a corresponding data bit from said B data set and having an exclusive OR output; (b) a comparator chain having N comparator circuits in series with a first comparator circuit at one end of said comparator chain and an Nth comparator circuit at the other end of said comparator chain, each of said comparator circuits comprising: (i) an output terminal; (ii) a first input coupled to one of the bits of said A data set, a second input coupled to one of said exclusive OR outputs, and a compare input, said compare input coupled to a reference voltage in said first commparator circuit, and the compare inputs of the remainder of said comparator circuits being coupled to the output terminal of the previous comparator circuit; (iii) switch circuitry which couples said first input to said output terminal when said second input is at a first logic state and which couples said compare input to said output terminal when said second input is at a second logic state; and (iv) wherein said output terminal of said Nth comparator circuit forms an output indicative of whether the A data set is greater than the B data set.
Claim 7
Dependent Claim
251 words
Circuitry for detecting if the number on a first data set, A, is greater than the number on a second data set, B, both of N bits in length, comprising: (a) an N plurality of exclusive OR gates, each of said exclusive OR gates having as inputs a data bit from said A data set and a corresponding data bit from said B data set and having an exclusive OR output; (b) a comparator chain having N comparator circuits in series with a first comparator circuit at one end of said comparator chain and an Nth comparator circuit at the other end of said comparator chain, each of said comparator circuits comprising: (i) an output terminal; (ii) a first input coupled to one of the bits of said A data set, a second input coupled to one of said exclusive OR outputs, and a compare input, said compare input coupled to a reference voltage in said first commparator circuit, and the compare inputs of the remainder of said comparator circuits being coupled to the output terminal of the previous comparator circuit; (iii) switch circuitry which couples said first input to said output terminal when said second input is at a first logic state and which couples said compare input to said output terminal when said second input is at a second logic state; and (iv) wherein said output terminal of said Nth comparator circuit forms an output indicative of whether the A data set is greater than the B data set.
Claim 8
Dependent Claim
194 words
Method for detecting if a first data set, A, is greater than a second data set, B, both data sets being of N bits in length, comprising the steps of: (a) exclusively ORing together each of the corresponding data bits of the A data set and the B data set; and (b) coupling a first input terminal of each of N comparator circuits to an output terminal of the comparator circuits when the output of a corresponding exclusive OR gate is a first logic state, and coupling a second input terminal of each of said comparator circuits to the output terminal when the output of said corresponding exclusive OR gate is a second logic state, said N comparator circuits formed in a series arrangement with a first comparator circuit having its first input terminal connected to a reference voltage and the input terminals of the rest of said comparator circuits connected to the output terminal of the previous comparator circuit in the chain, the output terminal of the Nth comparator circuit forming a signal indicative of whether the number on the A data bus is greater than the number on the B data bus.
Claim 9
Dependent Claim
194 words
Method for detecting if a first data set, A, is greater than a second data set, B, both data sets being of N bits in length, comprising the steps of: (a) exclusively ORing together each of the corresponding data bits of the A data set and the B data set; and (b) coupling a first input terminal of each of N comparator circuits to an output terminal of the comparator circuits when the output of a corresponding exclusive OR gate is a first logic state, and coupling a second input terminal of each of said comparator circuits to the output terminal when the output of said corresponding exclusive OR gate is a second logic state, said N comparator circuits formed in a series arrangement with a first comparator circuit having its first input terminal connected to a reference voltage and the input terminals of the rest of said comparator circuits connected to the output terminal of the previous comparator circuit in the chain, the output terminal of the Nth comparator circuit forming a signal indicative of whether the number on the A data bus is greater than the number on the B data bus.
Claim 10
Dependent Claim
249 words
Circuitry for detecting if the number on a first data set, A, is equal to the number on a second data set, B, both of N bits in length, comprising: (a) an N plurality of exclusive OR gates, each of said exclusive OR gates having as inputs a data bit from said A data set and a corresponding data bit from said B data set and having an exclusive OR output; (b) a comparator chain having N comparator circuits in series with a first comparator circuit at one end of said comparator chain and an Nth comparator circuit at the other end of said comparator chain, each of said comparator circuits comprising: (i) an output terminal; (ii) a first input coupled to a first logic level voltage, a second input coupled to one of said exclusive OR outputs, and a compare input, said compare input coupled to a second logic level voltage in said first comparator circuit, and the compare inputs of the remainder of said comparator circuits being coupled to the output terminal of the previous comparator circuit; (iii) switch circuitry which couples said first input to said output terminal when said second input is at a first logic state and which couples said compare input to said output terminal when said second input is at a second logic state; and (iv) wherein said output terminal of said Nth comparator circuit forms an output indicative of whether the A data set is equal to the B data set.
Claim 11
Dependent Claim
249 words
Circuitry for detecting if the number on a first data set, A, is equal to the number on a second data set, B, both of N bits in length, comprising: (a) an N plurality of exclusive OR gates, each of said exclusive OR gates having as inputs a data bit from said A data set and a corresponding data bit from said B data set and having an exclusive OR output; (b) a comparator chain having N comparator circuits in series with a first comparator circuit at one end of said comparator chain and an Nth comparator circuit at the other end of said comparator chain, each of said comparator circuits comprising: (i) an output terminal; (ii) a first input coupled to a first logic level voltage, a second input coupled to one of said exclusive OR outputs, and a compare input, said compare input coupled to a second logic level voltage in said first comparator circuit, and the compare inputs of the remainder of said comparator circuits being coupled to the output terminal of the previous comparator circuit; (iii) switch circuitry which couples said first input to said output terminal when said second input is at a first logic state and which couples said compare input to said output terminal when said second input is at a second logic state; and (iv) wherein said output terminal of said Nth comparator circuit forms an output indicative of whether the A data set is equal to the B data set.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |