Patent US3772774A successfully refreshed from Google Patents.
US3576531A
Expired / Lapsed
US
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Comparator circuit arrangement
Assignee: Applied Biosystems Inc
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Filing: 1966-05-27
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Granted: 1971-04-27
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Expires: 1986-05-27
Abstract
Abstract Circuit means are provided for converting a first number A which occurs in digital form to a first plurality of analog representations and a second number B which occurs in digital form to a second plurality of analog representations; for comparing the amplitude of the numbers in analog form; for providing a plurality of digital representations indicative of these relative analog magnitudes; and for comparing the digital representations thereby providing an indication as to the relative magnitudes of the numbers A and B.
Inventors
- 👤 Larkin B Scott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 16:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/02; G06F7/026; G06J; G06J1/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
173 words
A comparator circuit arrangement comprising: first and second resistive summing networks for summing a plurality of digital voltages applied to each network and for providing equivalent analog output voltages, means for applying a plurality of digital voltages representing a first number A to said first resistive network and a plurality of digital voltages representing a second number B to said second resistive network, first and second emitter follower amplifier stages and a differential amplifier having first and second transistor amplifying devices, means coupling said first and second resistive networks to said first and second emitter follower amplifiers respectively, means coupling an output voltage from said first emitter follower amplifier to base and emitter electrodes of said first and second transistor amplifying devices respectively, means coupling an output voltage from said second emitter follower amplifier to emitter and base electrode of said first and second transistor amplifying devices respectively, and said resistive networks and amplifier stages arranged for providing a digital output voltage indicative of the relative magnitudes of the numbers A and B.
Claim 2
Dependent Claim
173 words
A comparator circuit arrangement comprising: first and second resistive summing networks for summing a plurality of digital voltages applied to each network and for providing equivalent analog output voltages, means for applying a plurality of digital voltages representing a first number A to said first resistive network and a plurality of digital voltages representing a second number B to said second resistive network, first and second emitter follower amplifier stages and a differential amplifier having first and second transistor amplifying devices, means coupling said first and second resistive networks to said first and second emitter follower amplifiers respectively, means coupling an output voltage from said first emitter follower amplifier to base and emitter electrodes of said first and second transistor amplifying devices respectively, means coupling an output voltage from said second emitter follower amplifier to emitter and base electrode of said first and second transistor amplifying devices respectively, and said resistive networks and amplifier stages arranged for providing a digital output voltage indicative of the relative magnitudes of the numbers A and B.
Claim 3
Dependent Claim
183 words
A comparator circuit arrangement comprising: first circuit means providing a plurality of output voltages representative of a first number A having n digits, second circuit means providing a plurality of output voltages representative of a second number B having n digits, third and fourth circuit means each adapted to convert first and second pluralities of digital voltages to first and second analog voltages respectively and for providing first and second digital output voltages indicative of the relative amplitudes of the analog voltages, means coupling a plurality of voltages representing less significant digits of said numbers A and B from said first and from said second circuit means respectively to said third circuit means and coupling a plurality of voltages representing more significant digits of said numbers A and B from said first and from said second circuit means to said fourth circuit means, a digital comparator circuit adapted to provide an output voltage indicative of the relative magnitude of a plurality of digital numbers applied thereto, and means coupling the digital voltages from said third and fourth circuit means to said comparator circuit.
Claim 4
Dependent Claim
183 words
A comparator circuit arrangement comprising: first circuit means providing a plurality of output voltages representative of a first number A having n digits, second circuit means providing a plurality of output voltages representative of a second number B having n digits, third and fourth circuit means each adapted to convert first and second pluralities of digital voltages to first and second analog voltages respectively and for providing first and second digital output voltages indicative of the relative amplitudes of the analog voltages, means coupling a plurality of voltages representing less significant digits of said numbers A and B from said first and from said second circuit means respectively to said third circuit means and coupling a plurality of voltages representing more significant digits of said numbers A and B from said first and from said second circuit means to said fourth circuit means, a digital comparator circuit adapted to provide an output voltage indicative of the relative magnitude of a plurality of digital numbers applied thereto, and means coupling the digital voltages from said third and fourth circuit means to said comparator circuit.
Claim 5
Dependent Claim
49 words
The comparator of claim 2 wherein said third and fourth circuit means each include first and second digital to analog voltage converters and a differential amplifier coupled to said converter and adapted to compare and provide a digital output voltage representative of the relative magnitude of said analog voltages.
Claim 6
Dependent Claim
147 words
The comparator of claim 2 wherein: said third circuit means provides digital output voltages EA when the less signifiCant digits of A represent a number larger than the less significant digits of B as an output voltage EB when the less significant digits of B represent a number larger than the less significant digits of A, said fourth circuit means provides a digital output voltage E''A when the more significant digits of A represent a number larger than the more significant digits of B and as output voltage E''B when the more significant digits of B represent a number larger than the more significant digits of B, and said digital comparator circuit includes a circuit arrangement for providing an output voltage EAO when the number A is larger than the number B and an output voltage EBO when the number B is larger than the number A.
Claim 7
Dependent Claim
27 words
The comparator of claim 4 wherein said digital comparator circuit is arranged to provide the output voltage EAO in accordance with the logical relation: EAO EA''+ (EA.EB'')
Claim 8
Dependent Claim
29 words
The comparator of claim 4 wherein said digital comparator circuit is arranged to provide the output voltage EAO in accordance with the logical relation: EAO EA''+ EA + EB''
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-26 | 1974-10-26 | 1975-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-26 | 1978-10-26 | 1979-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-26 | 1982-10-26 | 1983-04-27 | $7700.00 | Window Closed / Lapsed |