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US4933576A
Expired / Lapsed
US
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Gate array device having macro cells for forming master and slave cells of master-slave flip-flop circuit
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1989-05-09
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Granted: 1990-06-12
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Expires: 2009-05-09
Abstract
Abstract A gate array device forms an arbitray logic circuit depending on interconnections formed thereon, and comprises a semiconductor chip having an approximate rectangular shape, an input terminal region including a plurality of input terminals formed at a peripheral portion of the semiconductor chip, an output terminal region including a plurality of output terminals formed at a peripheral portion of the semiconductor chip, and a macro cell region including a plurality of macro cells formed at a central portion of the semiconductor chip. The macro cells include first macro cells and second macro cells, where each of the first macro cells include a minimum number of elements for forming a master part of a master-slave flip-flop circuit and each of the second macro cells include at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit. The first macro cells and the second macro cells make macro cell pairs and are regularly arranged within the macro cell region.
Inventors
- 👤 Masaya Tamamura
- 👤 Shinji Emori
- 👤 Yoshio Watanabe
- 👤 Isao Shimotsuhama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/08; H03K19/082; H03K19/086; H03K19/0866; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0372; Y; Y10; Y10S; Y10S257/00; Y10S257/923
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
165 words
A gate array device which forms an arbitrary logic circuit depending on interconnections formed thereon, said gate array device comprising: a semiconductor chip having an approximate rectangular shape; an input terminal region including a plurality of input terminals formed at a peripheral portion of said semiconductor chip; an output terminal region including a plurality of output terminals formed at a peripheral portion of said semiconductor chip; and a macro cell region including a plurality of macro cells formed at a central portion of said semiconductor chip, said macro cells including first macro cells and second macro cells, each of said first macro cells including a minimum number of elements for forming a master part of a master-slave flip-flop circuit, each of said second macro cells including at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit, said first macro cells and said second macro cells making macro cell pairs and being regularly arranged within said macro cell region.
Claim 2
Dependent Claim
165 words
A gate array device which forms an arbitrary logic circuit depending on interconnections formed thereon, said gate array device comprising: a semiconductor chip having an approximate rectangular shape; an input terminal region including a plurality of input terminals formed at a peripheral portion of said semiconductor chip; an output terminal region including a plurality of output terminals formed at a peripheral portion of said semiconductor chip; and a macro cell region including a plurality of macro cells formed at a central portion of said semiconductor chip, said macro cells including first macro cells and second macro cells, each of said first macro cells including a minimum number of elements for forming a master part of a master-slave flip-flop circuit, each of said second macro cells including at least a minimum number of elements for forming a slave part of the master-slave flip-flop circuit, said first macro cells and said second macro cells making macro cell pairs and being regularly arranged within said macro cell region.
Claim 3
Dependent Claim
34 words
The gate array device as claimed in claim 1 wherein said macro cell region includes a row of said first macro cells and a row of said second macro cells which are alternately arranged.
Claim 4
Dependent Claim
59 words
The gate array device as claimed in claim 1 wherein said macro cell region includes a repetition of a basic row pattern, said basic row pattern being made up of a row of said first macro cells, a row of said second macro cells, a row of said second macro cells, and a row of said first macro cells.
Claim 5
Dependent Claim
45 words
The gate array device as claimed in claim 1 wherein said macro cell region is made up of a first region and a second region which are bounded on a boundary, said first and second macro cells having a form symmetrical arrangement about the boundary.
Claim 6
Dependent Claim
33 words
The gate array device as claimed in claim 1 wherein said macro cells further includes third macro cells, said first through third macro cells having a regular arrangement within said macro cell region.
Claim 7
Dependent Claim
31 words
The gate array device as claimed in claim 5 wherein each of said third macro cells include at least a minimum number of elements for forming a bias voltage source circuit.
Claim 8
Dependent Claim
58 words
The gate array device as claimed in claim 1 wherein said semiconductor chip sequentially has first through fourth sides, said input terminal region being arranged at least along the first side of said semiconductor chip, said output terminal region being arranged at least along the third side of said semiconductor chip, said first side confronting said third side.
Claim 9
Dependent Claim
44 words
The gate array device as claimed in claim 7 wherein said first and second macro cells have inputs on a side thereof facing the first side of said semiconductor chip and outputs on a side thereof facing the third side of said semiconductor chip.
Claim 10
Dependent Claim
33 words
The gate array device as claimed in claim 7 wherein said input terminal region is arranged continuously along the first side and portions of the second and fourth sides of said semiconductor chip.
Claim 11
Dependent Claim
33 words
The gate array device as claimed in claim 7 wherein said output terminal region is arranged continuously along the third side and portions of the second and fourth sides of said semiconductor chip.
Claim 12
Dependent Claim
69 words
The gate array device as claimed in claim 7 wherein said input terminal region has an approximate U-shape arranged along the first side and portions of the second and fourth sides of said semiconductor chip and said output terminal region has an approximate U-shape arranged along the third side and portions of the second and fourth sides so as to confront the approximate U-shape of said input terminal region.
Claim 13
Dependent Claim
26 words
The gate array device as claimed in claim 11 wherein said macro cell region is substantially located within the approximate U-shape of said input terminal region.
Claim 14
Dependent Claim
70 words
The gate array device as claimed in claim 12 wherein said cell region is made up of a first region and a second region bounded on a boundary, said first region being arranged close to the second side of said semiconductor chip, said second region being arranged close to the fourth side of said semiconductor chip, said first and second macro cells having a form symmetrical arrangement about the boundary.
Claim 15
Dependent Claim
48 words
The gate array device as claimed in claim 12 which further comprises an output buffer region including a plurality of output buffers, said output buffer region being substantially located within the approximate U-shape of said output terminal region between said macro cell region and said output terminal region.
Claim 16
Dependent Claim
29 words
The gate array device as claimed in claim 7 wherein at least one of said input terminal region and said output terminal region further includes power source voltage terminals.
Claim 17
Dependent Claim
40 words
The gate array device as claimed in claim 7 which further comprises a power source terminal region formed between said input terminal region and said output terminal region, said power source terminal region including at least one power source terminal.
Claim 18
Dependent Claim
51 words
The gate array device as claimed in claim 7 wherein said semiconductor chip sequentially has first through fourth sides, said input terminal region being arranged along the first and second sides of said semiconductor chip, said output terminal region being arranged along the third and fourth sides of said semiconductor chip.
Claim 19
Dependent Claim
56 words
The gate array device as claimed in claim 17 which further comprises an output buffer region including a plurality of output buffers, said output buffer region being substantially located along said output terminal region, each of the output buffers of said output buffer region corresponding to one of the output terminals of said output terminal region.
Claim 20
Dependent Claim
36 words
The gate array device as claimed in claim 1 wherein each of said first macro cells occupy within said macro cell region an area greater than an area occupied by each of said second macro cells.
Claim 21
Dependent Claim
44 words
The gate array device as claimed in claim 1 which further comprises an interconnection region formed between said macro cell region and said output terminal region of said semiconductor chip, said interconnection region being formed with non-intersecting interconnections when forming the arbitrary logic circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |