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US4933571A
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Synchronizing flip-flop circuit configuration
Assignee: Siemens AG
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Filing: 1988-08-15
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Granted: 1990-06-12
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Expires: 2008-08-15
Abstract
Abstract A synchronizing flip-flop circuit configuration for synchronizing data includes an input and an output of the synchronizing flip-flop circuit configuration. A first transfer gate, connected to the input of the synchronizing flip-flop circuit configuration, is controlled by a first clock signal. A second transfer gate connected between the first transfer gate and the output of the synchronizing flip-flop circuit configuration is controlled by a second clock signal being inverted with respect to the first clock signal. A first series-connected inverter pair is connected between the first transfer gate and the output of the synchronizing flip-flop circuit configuration. At least one second inverter series-connected inverter pair is connected in series with the first inverter configuration between the first transfer gate and the output of the synchronizing flip-flop circuit configuration, thereby preventing occurrence of meta-stable conditions between data to be synchronized.
Inventors
- 👤 Wolfgang Pribyl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:25
CPC Classifications
H; H03; H03K; H03K19/00; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375; H03K3/353; H03K3/356; H03K3/356104
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
131 words
Synchronizing flip-flop circuit configuration having an input connected to a data signal and an output, comprising a first transfer gate having an input connected to said data signal, and an output, a clock signal controlling said first transfer gate and an inverted clock signal complementary to said clock signal, a first pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration, a second transfer gate connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration controlled by said inverted clock signal, and at least one further pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration in series with said first pair of series-connected inverters.
Claim 2
Dependent Claim
131 words
Synchronizing flip-flop circuit configuration having an input connected to a data signal and an output, comprising a first transfer gate having an input connected to said data signal, and an output, a clock signal controlling said first transfer gate and an inverted clock signal complementary to said clock signal, a first pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration, a second transfer gate connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration controlled by said inverted clock signal, and at least one further pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration in series with said first pair of series-connected inverters.
Claim 3
Dependent Claim
15 words
Synchronizing flip-flop circuit configuration according to claim 1, wherein said inverter pairs contain CMOS inverters.
Claim 4
Dependent Claim
33 words
Synchronizing flip-flop circuit configuration according to claim 1, wherein at least one of said transfer gates has two parallel channels each channel including transistors of a conductivity type being complementary to each other.
Claim 5
Dependent Claim
141 words
Synchronizing flip-flop circuit configuration having an input connected to a data signal and an output, comprising a first transfer gate having an input connected to said data signal, and an output, a first pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration, a second transfer gate connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration, a clock signal controlling said first and second transfer gate, at least one further pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration in series with said first pair of series-connected inverters; and wherein said first transfer gate contains transistors of only one conductivity type, and said second transfer gate contains transistors of only opposite conductivity type.
Claim 6
Dependent Claim
141 words
Synchronizing flip-flop circuit configuration having an input connected to a data signal and an output, comprising a first transfer gate having an input connected to said data signal, and an output, a first pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration, a second transfer gate connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration, a clock signal controlling said first and second transfer gate, at least one further pair of series-connected inverters connected between said first transfer gate output and said output of the synchronizing flip-flop circuit configuration in series with said first pair of series-connected inverters; and wherein said first transfer gate contains transistors of only one conductivity type, and said second transfer gate contains transistors of only opposite conductivity type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-11 | 1993-12-11 | 1994-06-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-11 | 1997-12-11 | 1998-06-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-11 | 2001-12-11 | 2002-06-12 | $7700.00 | Window Closed / Lapsed |