US4928160A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate isolated base cell structure with off-grid gate polysilicon pattern
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1989-01-17
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Granted: 1990-05-22
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Expires: 2009-01-17
Abstract
Abstract A CMOS gate isolated gate array configured with a single polysilicon layer and preferably two metallization layers, wherein the cell pitch is equal to the first and second metallization pitches by referencing the metallization layers, contacts and vias to a grid, and referencing the polysilicon layer to a half grid. Further refinements include the use of channel regions between parallel and adjacent chains of complementary transistors, wherein the width of the channel is equal to three times the pitch of the cell. In another form, a base set of the gate array includes diffused resistors in the channel regions suitable for matching discretionary interconnection.
Inventors
- 👤 Harold S. Crafts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
74 words
A two metal layer integrated circuit gate array configured from a chain of polysilicon gate isolated field effect transistors, comprising: a grid reference to the source/drain regions of the field effect transistors; a first metal layer pattern referenced to the grid; a second metal layer pattern referenced to the grid; a source/drain contact referenced to the grid; an intermetal via referenced to the grid; and a gate polysilicon pattern referenced to the half grid.
Claim 2
Dependent Claim
74 words
A two metal layer integrated circuit gate array configured from a chain of polysilicon gate isolated field effect transistors, comprising: a grid reference to the source/drain regions of the field effect transistors; a first metal layer pattern referenced to the grid; a second metal layer pattern referenced to the grid; a source/drain contact referenced to the grid; an intermetal via referenced to the grid; and a gate polysilicon pattern referenced to the half grid.
Claim 3
Dependent Claim
25 words
The apparatus recited in claim 1, wherein the gate polysilicon contact region is displaced relatively to the gate electrode defining the field effect transistor channel.
Claim 4
Dependent Claim
36 words
The apparatus recited in claim 2, wherein the pitch of the gate polysilicon pattern, the contact pattern, the via pattern, the first metal layer pattern, and the second metal layer pattern are substantially equal in magnitude.
Claim 5
Dependent Claim
34 words
The apparatus recited in claim 3, wherein the minimum gate polysilicon spacing and first metal layer spacing are one grid, and the minimum contact width, vias width and gate polysilicon width are one grid.
Claim 6
Dependent Claim
26 words
The apparatus recited in claim 4, wherein contacts and vias are defined within two grid dimension regions of source/drain, gate polysilicon, first metal or second metal.
Claim 7
Dependent Claim
44 words
A two metal layer integrated circuit gate array configured with polysilicon gate isolated field effect transistors in chains of adjacent and complementary pairs, characterized by the presence of channel regions between adjacent chain pairs having a channel width suitable to form three metal lines.
Claim 8
Dependent Claim
44 words
A two metal layer integrated circuit gate array configured with polysilicon gate isolated field effect transistors in chains of adjacent and complementary pairs, characterized by the presence of channel regions between adjacent chain pairs having a channel width suitable to form three metal lines.
Claim 9
Dependent Claim
31 words
The apparatus recited in claim 6, wherein the channel regions contain matched resistive elements diffused into the integrated circuit gate array substrate and extend in a direction parallel to the channel.
Claim 10
Dependent Claim
19 words
The apparatus recited in claim 7, wherein the diffused resistive elements are comparable in width to the metal lines.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-21 | 1993-11-20 | 1994-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-21 | 1997-11-20 | 1998-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-21 | 2001-11-20 | 2002-05-22 | $7700.00 | Window Closed / Lapsed |