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US4926385A
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Semiconductor memory device with cache memory addressable by block within each column
Assignee: Mitsubishi Electric Corp
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Filing: 1988-08-05
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Granted: 1990-05-15
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Expires: 2008-08-05
Abstract
Abstract A semiconductor memory includes a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines. A plurality of memory cells are arranged at intersections of the bit lines and the word lines, respectively. Word line selecting circuitry selects one of the word lines responsive to a row address and reads out to each of the bit lines information stored in the memory cell associated with the selected word line. A plurality of sense amplifiers are associated with corresponding rows of the memory for detecting and amplifying the information stored in respective memory cells. A first column selector circuit selects the sense amplifiers corresponding to a column address when the column address is applied and reads information held in the sense amplifier. Blocks are formed by dividing the memory cell array into groups of bit lines, each of the groups comprising a predetermined number of bit lines with block information transferred simultaneously from corresponding ones of the groups of bit lines of a selected block when the column address corresponding to the selected block is applied. Data registers hold information of an associated block. A second column selector reads data corresponding to the column address from the data register when the column address is applied.
Inventors
- 👤 Kazuyasu Fujishima
- 👤 Hideto Hidaka
- 👤 Mikio Asakura
- 👤 Yoshio Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 14:45
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0893; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
282 words
A semiconductor memory device for a simple cache system, comprising: a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines, a plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively, address inputting means for receiving a row address and a column address, word line selecting means responsive to said row address for selecting one of said word lines, to read out to each of said bit lines information stored in respective ones of said memory cells associated with the selected word line, a plurality of sense amplifiers for detecting and amplifying the information stored in respective ones of said memory cells corresponding to one row read out to each of said bit lines, first column selecting means for selecting the sense amplifiers corresponding to a column address when the column address is applied, to read out information held in the sense amplifier, a plurality of block information transferring means each provided in each of blocks obtained by dividing said memory cell array into groups of said bit lines, each of said groups comprising a predetermined number of said bit lines, said block information transferring means for simultaneously transferring information from a corresponding one of said groups of bit lines of a selected blocks in response to application of said column address corresponding to the selected block, a plurality of data registers for storing, for each respective block, information transferred by each of said block information transferring means, and second column selecting means for reading out data corresponding to the column address from said data register in response to application of said column address.
Claim 2
Dependent Claim
282 words
A semiconductor memory device for a simple cache system, comprising: a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines, a plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively, address inputting means for receiving a row address and a column address, word line selecting means responsive to said row address for selecting one of said word lines, to read out to each of said bit lines information stored in respective ones of said memory cells associated with the selected word line, a plurality of sense amplifiers for detecting and amplifying the information stored in respective ones of said memory cells corresponding to one row read out to each of said bit lines, first column selecting means for selecting the sense amplifiers corresponding to a column address when the column address is applied, to read out information held in the sense amplifier, a plurality of block information transferring means each provided in each of blocks obtained by dividing said memory cell array into groups of said bit lines, each of said groups comprising a predetermined number of said bit lines, said block information transferring means for simultaneously transferring information from a corresponding one of said groups of bit lines of a selected blocks in response to application of said column address corresponding to the selected block, a plurality of data registers for storing, for each respective block, information transferred by each of said block information transferring means, and second column selecting means for reading out data corresponding to the column address from said data register in response to application of said column address.
Claim 3
Dependent Claim
46 words
The semiconductor memory device according to claim 1, which further comprises switching means responsive to a first control signal externally inputted for performing a switching operation depending on whether said column address is supplied to said first column selecting means or said second column selecting means.
Claim 4
Dependent Claim
37 words
The semiconductor memory device according to claim 2, wherein said first control signal is a cache hit signal indicating that information stored in said memory cell to be accessed this time is held in said data register
Claim 5
Dependent Claim
34 words
The semiconductor memory device according to claim 3, wherein said switching means supplies the column address to said block information transferring means when said column address is supplied to said first column selecting means.
Claim 6
Dependent Claim
37 words
The semiconductor memory device according to claim 4, which further comprises gate means responsive to a second control signal externally applied for gating the column address supplied to said block information transferring means from said switching means.
Claim 7
Dependent Claim
30 words
The semiconductor memory device according to claim 5, wherein said second control signal is a rewrite permit signal indicating that rewriting of information stored in said data register is permitted.
Claim 8
Dependent Claim
274 words
A semiconductor memory device including a high-speed cache system, comprising: a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines, said memory array divided into a plurality of blocks obtained by dividing said memory cell array into groups of said bit lines, each of said groups comprising a predetermined number of said bit lines; a plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively, address inputting means for receiving a row address and a column address, word line selecting means responsive to said row address for selecting one of said word lines for transferring to each of said bit lines information stored in respective ones of said memory cells associated with the selected word line, a plurality of sense amplifiers for detecting and amplifying the information stored in respective ones of said memory cells corresponding to one row read out to each of said bit lines, first column selecting means for selecting sense amplifiers corresponding to a column address in response to application of the column address, to read out information held in the sense amplifier, block information transferring means for simultaneously transferring information from a corresponding one of said groups of bit lines of a selected block in response to application of said column address corresponding to the selected block, a plurality of data registers for storing, for each block, information transferred by said block information transferring means, and second column selecting means for reading out data corresponding to the column address from said data register in response to application of said column address.
Claim 9
Dependent Claim
274 words
A semiconductor memory device including a high-speed cache system, comprising: a memory cell array having a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines, said memory array divided into a plurality of blocks obtained by dividing said memory cell array into groups of said bit lines, each of said groups comprising a predetermined number of said bit lines; a plurality of memory cells arranged at intersections of the bit lines and the word lines, respectively, address inputting means for receiving a row address and a column address, word line selecting means responsive to said row address for selecting one of said word lines for transferring to each of said bit lines information stored in respective ones of said memory cells associated with the selected word line, a plurality of sense amplifiers for detecting and amplifying the information stored in respective ones of said memory cells corresponding to one row read out to each of said bit lines, first column selecting means for selecting sense amplifiers corresponding to a column address in response to application of the column address, to read out information held in the sense amplifier, block information transferring means for simultaneously transferring information from a corresponding one of said groups of bit lines of a selected block in response to application of said column address corresponding to the selected block, a plurality of data registers for storing, for each block, information transferred by said block information transferring means, and second column selecting means for reading out data corresponding to the column address from said data register in response to application of said column address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |