EP0167089A2
Expired / Lapsed
EP
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Memory access control system and method for an information processing apparatus
Assignee: Hitachi Ltd
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Filing: 1985-06-25
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Granted: —
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Expires: 2005-06-25
Abstract
Abstract There is a memory access control system for an information processing apparatus having a buffer memory (300) and a main memory (500). In this system, when a store or access request is generated, in the case where the data block in the address to be accessed does not exist in the buffer memory (300), the store requested data from a data register (3) is written into the buffer memory (300) before the first data in the data block read out from the main memory (500) is written into the buffer memory (300), and the data register is released to receive the next request.
Inventors
- 👤 Toshihisa Taniguchi
- 👤 Tsutomu Sumimoto
- 👤 Takashi Kumagai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 05:56
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
333 words
A memory access control system for an information processing apparatus comprising: a first memory (500) divided into a plurality of blocks; a second memory (300) for storing a duplicate of partial data stored in said first memory (500) on a block unit basis, said second memory (300) being able to be accessed at a higher speed than said first memory and having a memory capacity smaller than that of said first memory; a data register (3) for temporarily holding a store-requested data; an address register (1) for temporarily holding the address of said store-requested data; discriminating means (5; 6a, 6b, 6c, 6d) for outputting a discrimination signal indicative of presence or absence in said second memory (300) regarding the duplicate of the data block including the data designated by the address in said address register (1); first memory access control means (22) for controlling a reading operation of data from said first memory (500) and a writing operation of data into the first memory (500); second memory access control means (21) for controlling a reading operation of data from said second memory (300) and a writing operation of data into the second memory (300); and third control means (14, 19) for supplying control signals to said first and second memory access control means (22 and 21) in response to the discrimination signal from said discriminating means (5; 6a, 6b, 6c, 6d) when a data store request is generated, so that the data in said data register (3) is written into the second memory (300) in the case where the duplicate of the data block corresponding to said data store request exists in said second memory and that the duplicate of the remaining data in said data block read out from the first memory (500) is written in the second memory after the data in said data register (3) was written into the second memory (300) in the case where the duplicate of said data block does not exist in the second memory (300).
Claim 2
Dependent Claim
333 words
A memory access control system for an information processing apparatus comprising: a first memory (500) divided into a plurality of blocks; a second memory (300) for storing a duplicate of partial data stored in said first memory (500) on a block unit basis, said second memory (300) being able to be accessed at a higher speed than said first memory and having a memory capacity smaller than that of said first memory; a data register (3) for temporarily holding a store-requested data; an address register (1) for temporarily holding the address of said store-requested data; discriminating means (5; 6a, 6b, 6c, 6d) for outputting a discrimination signal indicative of presence or absence in said second memory (300) regarding the duplicate of the data block including the data designated by the address in said address register (1); first memory access control means (22) for controlling a reading operation of data from said first memory (500) and a writing operation of data into the first memory (500); second memory access control means (21) for controlling a reading operation of data from said second memory (300) and a writing operation of data into the second memory (300); and third control means (14, 19) for supplying control signals to said first and second memory access control means (22 and 21) in response to the discrimination signal from said discriminating means (5; 6a, 6b, 6c, 6d) when a data store request is generated, so that the data in said data register (3) is written into the second memory (300) in the case where the duplicate of the data block corresponding to said data store request exists in said second memory and that the duplicate of the remaining data in said data block read out from the first memory (500) is written in the second memory after the data in said data register (3) was written into the second memory (300) in the case where the duplicate of said data block does not exist in the second memory (300).
Claim 3
Dependent Claim
149 words
A system according to claim 1, wherein said second memory (300) has a data memory area as much as a plurality of blocks; said discriminating means has fourth means (7) for generating a position information to designate the area in the second memory (300) in order to store the duplicate of said data block read out from said first memory (500) in the case where the duplicate of the data block including the data designated by the address in said address register (1) does not exist in the second memory (300); and said second memory (300) writes the data from said data register (3) and the remaining data in one block from the first memory (500) within the range of the memory area specified by said position information from the address, as a start point, that is determined by a part of the content of said address register (1).
Claim 4
Dependent Claim
92 words
A system according to claim 2, wherein said system further includes means (23) for correcting an address value outputted from said address register (1) in accordance with the length of said store registered data, and wherein said first memory (500) sequentially reads out the remaining data in one data block excluding the data stored from said data register (3) from said corrected address as a start point, and said second memory (300) stores the data from said first memory (500) subsequently to the storage of the data from said data register (3).
Claim 5
Dependent Claim
190 words
A system according to claim 2, wherein said discriminating means (5; 6a, 6b, 6c, 6d) has fifth means (8) in which, for every data block existing in said second memory (300), indication information representing whether or not it is necessary to write said data block into the first memory (500) is stored and which outputs said indication information corresponding to the data block that is designated by said position information in the case where the duplicate of the data block including the data designated by the address in said address register (1) does not exist in the second memory (300), and said third control means (14, 19) supplies control signals to said first and second memory access control means (22 and 21) in accordance with said indication information when the data store request is generated in a manner such that the data in said data register (3) is written into the second memory (300) and the data is written from the first memory (500) into the second memory (300) after the data block in the second memory that is designated by said position information was written into the first memory.
Claim 6
Dependent Claim
91 words
A system according to claim 4, which further has means (23) for correcting an address value outputted from said address register (1) in accordance with the length of said store requested data, and in which said first memory (500) sequentially reads out the remaining data in one data block excluding the data stored from said data register (3) from said corrected address as a start point, and said second memory (300) stores the data from said first memory (500) subsequently to the storage of the data from said data register (3).
Claim 7
Dependent Claim
212 words
A memory access method for an information processing apparatus having a first memory (500) divided into a plurality of blocks and a second memory (300) for storing a duplicate of partial data stored in said first memory (500) on a block unit basis, said second memory (300) being able to be accessed at a higher speed than said first memory (500), comprising: a first step of discriminating presence or absence in said second memory with regard to the duplicate of the data block corresponding to the store address when a data store request is generated; a second step of designating the area in the second memory (300) for storage of the duplicate of said data block in the case where it is determined that the duplicate of the data block corresponding to the store address does not exist in the second memory in the first step; a third step of writing said store requested data into said designated area in the second memory prior to transferring the data block from the first memory (500) into the second memory (300); and a fourth step of writing the remaining data in one data block read out from the first memory excluding said store requested data into said designated area in the second memory (300).
Claim 8
Dependent Claim
212 words
A memory access method for an information processing apparatus having a first memory (500) divided into a plurality of blocks and a second memory (300) for storing a duplicate of partial data stored in said first memory (500) on a block unit basis, said second memory (300) being able to be accessed at a higher speed than said first memory (500), comprising: a first step of discriminating presence or absence in said second memory with regard to the duplicate of the data block corresponding to the store address when a data store request is generated; a second step of designating the area in the second memory (300) for storage of the duplicate of said data block in the case where it is determined that the duplicate of the data block corresponding to the store address does not exist in the second memory in the first step; a third step of writing said store requested data into said designated area in the second memory prior to transferring the data block from the first memory (500) into the second memory (300); and a fourth step of writing the remaining data in one data block read out from the first memory excluding said store requested data into said designated area in the second memory (300).
Claim 9
Dependent Claim
45 words
A method according to claim 6, wherein only the remaining data in one data block is read out from said first memory (500) in order to sequentially write from the data in the next address of said store requested data into said second memory (300).
References Cited (Backward Citations)
No citation records indexed.
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