Patent US4926115A successfully refreshed from Google Patents.
US4926115A
Expired / Lapsed
US
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Unique phase difference measuring circuit
Assignee: GTE Communication Systems Corp
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Filing: 1988-12-19
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Granted: 1990-05-15
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Expires: 2008-12-19
Abstract
Abstract A Unique Phase Difference Measuring Circuit which measures the phase difference between a reference pulse train and a slave pulse train. The present invention includes delay lines that determine the phase difference between the pulse trains which can be read directly by a microprocessor.
Inventors
- 👤 George K. Tarleton
- 👤 Robert J. Abrant
- 👤 Bruce A. Oltman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:54
CPC Classifications
G; G01; G01R; G01R25/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
427 words
A phase difference measuring circuit for measuring the phase difference between a first pulse train and a second pulse train, said phase difference measuring circuit comprising: timing circuit means arranged to output timing signals in response to a received start phase measurement signal; first and second clock buffer means, said first clock buffer means including a first input connected to said first pulse train, a second input connected to said timing signals and an output, and responsive to said first clock buffer means receiving said timing signal said first clock buffer means transmits said first pulse train from said output; first delay line means for delaying said first pulse train, including an input connected to the output of said first clock buffer means, said first delay line means including a plurality of outputs, said outputs arranged to transmit signals representing a value of delay of said first pulse train; first holding register means including a pulse train receiving input and a plurality of holding register inputs, said pulse train receiving input connected to said second clock buffer means output, and said plurality of holding register inputs connected to said plurality of outputs of said first delay line means, said holding register means arranged to latch the value of delay output by said first delay line means when said second pulse train changes logic level, and store the last delay measurement with respect to said second pulse train; said second clock buffer means including a first input connected to said second pulse train, a second input connected to said timing signals and an output, and responsive to said second clock buffer means receiving said timing signal said second clock buffer means transmits said second pulse train from said output; second delay line means for delaying said second pulse train, including an input connected to the output of said second clock buffer means, said second delay line means including a plurality of outputs, said outputs arranged to transmit signals representing a value of delay of said second pulse train, and; second holding register means including a pulse train receiving input and a plurality of holding register inputs, said pulse train receiving input connected to said first clock buffer means output, and said plurality of holding register inputs connected to said plurality of outputs of said second delay line means, said holding register means arranged to latch the value of delay output by said second delay line means outputs when said second pulse train changes logic level, and store the last delay measurement with respect to said first pulse train.
Claim 2
Dependent Claim
427 words
A phase difference measuring circuit for measuring the phase difference between a first pulse train and a second pulse train, said phase difference measuring circuit comprising: timing circuit means arranged to output timing signals in response to a received start phase measurement signal; first and second clock buffer means, said first clock buffer means including a first input connected to said first pulse train, a second input connected to said timing signals and an output, and responsive to said first clock buffer means receiving said timing signal said first clock buffer means transmits said first pulse train from said output; first delay line means for delaying said first pulse train, including an input connected to the output of said first clock buffer means, said first delay line means including a plurality of outputs, said outputs arranged to transmit signals representing a value of delay of said first pulse train; first holding register means including a pulse train receiving input and a plurality of holding register inputs, said pulse train receiving input connected to said second clock buffer means output, and said plurality of holding register inputs connected to said plurality of outputs of said first delay line means, said holding register means arranged to latch the value of delay output by said first delay line means when said second pulse train changes logic level, and store the last delay measurement with respect to said second pulse train; said second clock buffer means including a first input connected to said second pulse train, a second input connected to said timing signals and an output, and responsive to said second clock buffer means receiving said timing signal said second clock buffer means transmits said second pulse train from said output; second delay line means for delaying said second pulse train, including an input connected to the output of said second clock buffer means, said second delay line means including a plurality of outputs, said outputs arranged to transmit signals representing a value of delay of said second pulse train, and; second holding register means including a pulse train receiving input and a plurality of holding register inputs, said pulse train receiving input connected to said first clock buffer means output, and said plurality of holding register inputs connected to said plurality of outputs of said second delay line means, said holding register means arranged to latch the value of delay output by said second delay line means outputs when said second pulse train changes logic level, and store the last delay measurement with respect to said first pulse train.
Claim 3
Dependent Claim
54 words
The phase difference measuring circuit as claimed in claim 1, wherein: said first clock buffer means comprises a NAND gate having an inverting output connected to said first delay line means, said NAND gate further including a first input connected to said first pulse train and a second input connected to said timing signals.
Claim 4
Dependent Claim
54 words
The phase difference measuring circuit as claimed in claim 1, wherein: said second clock buffer means comprises a NAND gate having an inverting output connected to said second delay line means, said NAND gate further including a first input connected to said second pulse train and a second input connected to said timing signals.
Claim 5
Dependent Claim
69 words
The phase difference measuring circuit as claimed in claim 1, wherein: said first delay line means comprises a delay line driver having an input connected to said first clock buffer output, said delay line driver including an output connected to the input of a multi-tap delay line, said multi-tap delay line having a plurality of outputs arranged to measure the value of delay of said multi-tap delay line input.
Claim 6
Dependent Claim
69 words
The phase difference measuring circuit as claimed in claim 1, wherein: said second delay line means comprises a delay line driver having an input connected to said second clock buffer output, said delay line driver including an output connected to the input of a multi-tap delay line, said multi-tap delay line having a plurality of outputs arranged to measure the value of delay of said multi-tap delay line input.
Claim 7
Dependent Claim
61 words
The phase difference measuring circuit as claimed in claim 1, wherein: said first holding register means comprises a plurality of Delay Flip-Flops (D-FF) having individual Delay (D) inputs connected to one of said plurality of outputs of said first delay means, said plurality of D-FFs further including a common clock input connected to the output of said second clock buffer means.
Claim 8
Dependent Claim
61 words
The phase difference measuring circuit as claimed in claim 1, wherein: said second holding register means comprises a plurality of Delay Flip-Flops (D-FF) having individual Delay (D) inputs connected to one of said plurality of outputs of said second delay means, said plurality of D-FFs further including a common clock input connected to the output of said first clock buffer means.
Claim 9
Dependent Claim
61 words
The phase difference measuring circuit as claimed in claim 4, wherein: said first holding register means comprises a plurality of Delay Flip-Flops (D-FF) having individual Delay (D) inputs connected to one of said plurality of outputs of said multi-tap delay line, said plurality of D-FFs further including a common clock input connected to the output of said second clock buffer means.
Claim 10
Dependent Claim
61 words
The phase difference measuring circuit as claimed in claim 5, wherein: said second holding register means comprises a plurality of Delay Flip-Flops (D-FF) having individual Delay (D) inputs connected to one of said plurality of outputs of said multi-tap delay line, said plurality of D-FFs further including a common clock input connected to the output of said first clock buffer means.
Claim 11
Dependent Claim
66 words
The phase difference measuring circuit as claimed in claim 1, wherein: said timing circuit means comprises a Delay Flip-Flop (D-FF) having the Delay (D) input connected to said start phase measurement signal, said Delay Flip-Flop including an output connected to synchronizing means, said synchronizing means arranged to generate said output timing signals simultaneously enabling both said first clock buffer means and said second clock buffer means.
Claim 12
Dependent Claim
288 words
A phase difference measuring circuit for measuring the phase difference between a first pulse train and a second pulse train, said phase difference measuring circuit comprising: timing circuit means arranged to output timing signals in response to a received start phase measurement signal; first and second clock buffer means, said first clock buffer means connected to said first pulse train and to said timing signals, and responsive to said timing signals said first clock buffer means transmits said first pulse train; first delay line means connected to said first clock buffer means, said first delay line means arranged to transmit signals representing a value of delay of said first pulse train; first holding register means connected to said second clock buffer means and to said first delay line means, said holding register means arranged to latch the value of delay output by said first delay line means when said second pulse train changes logic level, and store the last delay measurement with respect to said second pulse train; said second clock buffer means connected to said second pulse train and to said timing signals, and responsive to said timing signals said second clock buffer means transmits said second pulse train; second delay line means connected to said second clock buffer means, said second delay line means arranged to transmit signals representing a value of delay of said second pulse train, and; second holding register means connected to said first clock buffer means and to said second delay line means, said holding register means arranged to latch the value of delay output by said second delay line means when said second pulse train changes logic level, and store the last delay measurement with respect to said first pulse train.
Claim 13
Dependent Claim
288 words
A phase difference measuring circuit for measuring the phase difference between a first pulse train and a second pulse train, said phase difference measuring circuit comprising: timing circuit means arranged to output timing signals in response to a received start phase measurement signal; first and second clock buffer means, said first clock buffer means connected to said first pulse train and to said timing signals, and responsive to said timing signals said first clock buffer means transmits said first pulse train; first delay line means connected to said first clock buffer means, said first delay line means arranged to transmit signals representing a value of delay of said first pulse train; first holding register means connected to said second clock buffer means and to said first delay line means, said holding register means arranged to latch the value of delay output by said first delay line means when said second pulse train changes logic level, and store the last delay measurement with respect to said second pulse train; said second clock buffer means connected to said second pulse train and to said timing signals, and responsive to said timing signals said second clock buffer means transmits said second pulse train; second delay line means connected to said second clock buffer means, said second delay line means arranged to transmit signals representing a value of delay of said second pulse train, and; second holding register means connected to said first clock buffer means and to said second delay line means, said holding register means arranged to latch the value of delay output by said second delay line means when said second pulse train changes logic level, and store the last delay measurement with respect to said first pulse train.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-14 | 1993-11-13 | 1994-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-14 | 1997-11-13 | 1998-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-14 | 2001-11-13 | 2002-05-15 | $7700.00 | Window Closed / Lapsed |