US4924439A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit
Assignee: Hitachi Ltd
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Filing: 1989-05-30
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Granted: 1990-05-08
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Expires: 2009-05-30
Abstract
Abstract In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.
Inventors
- 👤 Katsumi Ogiue
- 👤 Yukio Suzuki
- 👤 Ikuro Masuda
- 👤 Masanori Odaka
- 👤 Hideaki Uchida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/411; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/06; G11C7/062; G11C7/1069; G11C7/1078; G11C7/1084; G11C7/1096; G11C7/12; G11C8/00; G11C8/06; G11C8/08; G11C8/10; G11C8/18; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
152 words
A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; selecting means coupled to receive a selecting signal and for selecting one of said plurality of storage means according to said selecting signal, said selecting means including a plurality of circuits coupled to one another, at least one circuit in said selecting means having an input stage comprised of a CMOS circuit, and an output stage comprised of a first bipolar transistor which executes at least one of charge and discharge of an output line of said at least one circuit; read-out means for reading out the information stored in said storage means selected by said selecting means, said read-out means including a second bipolar transistor responsive to the information to be read out; and control means coupled to said read-out means and responsive to a control signal and for controlling a read-out operation of said read-out means.
Claim 2
Dependent Claim
152 words
A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; selecting means coupled to receive a selecting signal and for selecting one of said plurality of storage means according to said selecting signal, said selecting means including a plurality of circuits coupled to one another, at least one circuit in said selecting means having an input stage comprised of a CMOS circuit, and an output stage comprised of a first bipolar transistor which executes at least one of charge and discharge of an output line of said at least one circuit; read-out means for reading out the information stored in said storage means selected by said selecting means, said read-out means including a second bipolar transistor responsive to the information to be read out; and control means coupled to said read-out means and responsive to a control signal and for controlling a read-out operation of said read-out means.
Claim 3
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 1, wherein each storage means includes at least one MIS element.
Claim 4
Dependent Claim
42 words
A semiconductor integrated circuit according to claim 1, wherein said output stage in said at least one circuit further includes a third bipolar transistor which executes the other of charge and discharge of said output line of said at least one circuit.
Claim 5
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 1, wherein said read-out means further includes a fourth bipolar transistor coupled to said second bipolar transistor so as to form a differential circuit.
Claim 6
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 1, further comprising: write-in means for writing information into the storage means selected by said selecting means, wherein said control means is further coupled to said write-in means and controls a write-in operation of said write-in means.
Claim 7
Dependent Claim
152 words
A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; selecting means coupled to receive a selecting signal and for selecting one of said plurality of storage means according to said selecting signal, read-out means for reading out the information stored in said storage means selected by said selecting means, said read-out means including a first bipolar transistor responsive to the information to be read out; and control means coupled to said read-out means and responsive to a control signal and for controlling a read-out operation of said read-out means, said control means including a plurality of circuits coupled to one another, at least one circuit in said control means having an input stage comprised of a CMOS circuit, and an output stage comprised of a second bipolar transistor which executes at least one of charge and discharge of an output line of said at least one circuit.
Claim 8
Dependent Claim
152 words
A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; selecting means coupled to receive a selecting signal and for selecting one of said plurality of storage means according to said selecting signal, read-out means for reading out the information stored in said storage means selected by said selecting means, said read-out means including a first bipolar transistor responsive to the information to be read out; and control means coupled to said read-out means and responsive to a control signal and for controlling a read-out operation of said read-out means, said control means including a plurality of circuits coupled to one another, at least one circuit in said control means having an input stage comprised of a CMOS circuit, and an output stage comprised of a second bipolar transistor which executes at least one of charge and discharge of an output line of said at least one circuit.
Claim 9
Dependent Claim
18 words
A semiconductor integrated circuit according to claim 6, wherein each storage means includes at least one MIS element.
Claim 10
Dependent Claim
42 words
A semiconductor integrated circuit according to claim 6, wherein said output stage in said at least one circuit further includes a third bipolar transistor which executes the other of charge and discharge of said output line of said at least one circuit.
Claim 11
Dependent Claim
31 words
A semiconductor integrated circuit according to claim 6, wherein said read-out means further includes a fourth bipolar transistor coupled to said second bipolar transistor so as to form a differential circuit.
Claim 12
Dependent Claim
44 words
A semiconductor integrated circuit according to claim 6, further comprising: write-in means for writing information into the storage means selected by said selecting means, wherein said control means is further coupled to said write-in means and controls a write-in operation of said write-in means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |