Semiconductor integrated circuit

Claim 2

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for respectively reading and writing information from and into said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said signal circuit includes a data output buffer for obtaining an information output signal, said data output buffer including a principal portion constructed of a CMOS circuit, and a plurality of bipolar transistors, which execute charge and discharge of gate capacitances of N-channel and P-channel output MISFETs of said data output buffer.

Claim 3

A semiconductor integrated circuit as defined in claim 1, wherein both said output MISFETs are controlled into a simultaneous "off" state by a data output buffer control signal.

Claim 4

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for respectively reading and writing information from and into said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said signal circuit includes a data input amplifier which supplies complementary signals to a common data line pair, said data input amplifier including a principal portion constructed of a CMOS circuit and at least one bipolar transistor, which executes at least one of charge and discharge of one of said common data line pair.

Claim 5

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for respectively reading and writing information from and into said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said signal circuit includes a data input amplifier which supplies complementary signals to a common data line pair, said data input amplifier including a principal portion constructed of a CMOS circuit and at least one bipolar transistor, which executes at least one of charge and discharge of one of said common data line pair.

Claim 6

A semiconductor integrated circuit as defined in claim 3, wherein input data is transmitted to an input terminal of said data input amplifier through a data input buffer which is constructed of said CMOS circuit.

Claim 7

A semiconductor integrated circuit comprising: an input node; an output node; first and second power supply terminals for supplying first and second power supply levels, respectively, to said semiconductor circuit; a first bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said output node; a second bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said output node; a first MOS transistor having a gate coupled to said input node; a second MOS transistor of opposite conductivity type to said first MOS transistor having a gate coupled to said input node, wherein said first and second MOS transistors are coupled in series with one another to have their respective source-drain paths coupled in series between said output node and said second power supply terminal to form a CMOS inverter circuit, and wherein a base of said second bipolar transistor is coupled to a junction between the respective source-drain paths of said first and second MOS transistors, and further wherein a base of said first bipolar transistor is coupled to said input node; a CMOS circuit having an input coupled to said input node and having first and second outputs coupled, respectively, to bases of said first and second bipolar transistors, wherein said CMOS circuit includes means for driving said first and second bipolar transistors in a push-pull mode of operation; and a discharge MOS transistor coupled to have a source-drain path coupled between a base of said second bipolar transistor and said second power supply terminal, said discharge MOS transistor also having a gate coupled to said first output of said CMOS circuit so that discharge of the base capacitance of said second bipolar transistor is controlled by said first output of said CMOS circuit which is coupled to the base of said first bipolar transistor, wherein said CMOS circuit includes a first MOS transistor of a first conductivity type having a gate coupled to said input node and having a source-drain path coupled between said first power supply terminal and said first CMOS circuit output, a second MOS transistor of a second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second power supply terminal and said first CMOS circuit output, and a third MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said output node and the second CMOS circuit output.

Claim 8

A semiconductor integrated circuit comprising: an input node; an output node; first and second power supply terminals for supplying first and second power supply levels, respectively, to said semiconductor circuit; a first bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said output node; a second bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said output node; a first MOS transistor having a gate coupled to said input node; a second MOS transistor of opposite conductivity type to said first MOS transistor having a gate coupled to said input node, wherein said first and second MOS transistors are coupled in series with one another to have their respective source-drain paths coupled in series between said output node and said second power supply terminal to form a CMOS inverter circuit, and wherein a base of said second bipolar transistor is coupled to a junction between the respective source-drain paths of said first and second MOS transistors, and further wherein a base of said first bipolar transistor is coupled to said input node; a CMOS circuit having an input coupled to said input node and having first and second outputs coupled, respectively, to bases of said first and second bipolar transistors, wherein said CMOS circuit includes means for driving said first and second bipolar transistors in a push-pull mode of operation; and a discharge MOS transistor coupled to have a source-drain path coupled between a base of said second bipolar transistor and said second power supply terminal, said discharge MOS transistor also having a gate coupled to said first output of said CMOS circuit so that discharge of the base capacitance of said second bipolar transistor is controlled by said first output of said CMOS circuit which is coupled to the base of said first bipolar transistor, wherein said CMOS circuit includes a first MOS transistor of a first conductivity type having a gate coupled to said input node and having a source-drain path coupled between said first power supply terminal and said first CMOS circuit output, a second MOS transistor of a second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second power supply terminal and said first CMOS circuit output, and a third MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said output node and the second CMOS circuit output.

Claim 9

A semiconductor integrated circuit according to claim 5, wherein said first bipolar transistor is coupled to have a collector coupled to said first power supply terminal and an emitter coupled to said output node, and said second bipolar transistor is coupled to have a collector coupled to said second output node and an emitter coupled to said second power supply terminal.

Claim 10

A semiconductor integrated circuit device according to claim 5, further comprising diode means coupled between said emitter collector path of said first bipolar transistor and said output node.

Claim 11

A semiconductor integrated circuit device comprising: an input node; an output node; first and second power supply terminals for supplying first and second power supply levels, respectively, to said semiconductor circuit; a first bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said output node; a second bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said output node; a CMOS circuit having an input coupled to said input node and having first and second outputs coupled, respectively, to bases of said first and second bipolar transistors, wherein said CMOS circuit includes means for driving said first and second bipolar transistors in a push-pull mode of operation; and a discharge MOS transistor coupled to have a source-drain path coupled between a base of said second bipolar transistor and said second power supply terminal, said discharge MOS transistor also having a gate coupled to said first output of said CMOS circuit so that discharge of the base capacitance of said second bipolar transistor is controlled by said first output of said CMOS circuit which is coupled to the base of said first bipolar transistor, and wherein said first bipolar transistor is coupled to have a collector coupled to said first power supply terminal and an emitter coupled to said output node, and said second bipolar transistor is coupled to have a collector coupled to said output node and an emitter coupled to said second power supply terminal, further comprising diode means coupled between said emitter-collector path of said first bipolar transistor and said output node.

Claim 12

A semiconductor integrated circuit device comprising: an input node; an output node; first and second power supply terminals for supplying first and second power supply levels, respectively, to said semiconductor circuit; a first bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said output node; a second bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said output node; a CMOS circuit having an input coupled to said input node and having first and second outputs coupled, respectively, to bases of said first and second bipolar transistors, wherein said CMOS circuit includes means for driving said first and second bipolar transistors in a push-pull mode of operation; and a discharge MOS transistor coupled to have a source-drain path coupled between a base of said second bipolar transistor and said second power supply terminal, said discharge MOS transistor also having a gate coupled to said first output of said CMOS circuit so that discharge of the base capacitance of said second bipolar transistor is controlled by said first output of said CMOS circuit which is coupled to the base of said first bipolar transistor, and wherein said first bipolar transistor is coupled to have a collector coupled to said first power supply terminal and an emitter coupled to said output node, and said second bipolar transistor is coupled to have a collector coupled to said output node and an emitter coupled to said second power supply terminal, further comprising diode means coupled between said emitter-collector path of said first bipolar transistor and said output node.

Claim 13

A semiconductor integrated circuit device according to claim 8, wherein said CMOS circuit includes a first MOS transistor of a first conductivity type having a gate coupled to said input node and having a source-drain path coupled between said first power supply terminal and said first CMOS circuit output, a second MOS transistor of a second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second power supply terminal and said first CMOS circuit output, and a third MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said output node and the second CMOS circuit output.

Claim 14

A semiconductor integrated circuit device according to claim 9, wherein said discharge MOS transistor is of said second conductivity type.

Claim 15

A semiconductor integrated circuit device according to claim 10, wherein said first conductivity type is a P-channel type, and wherein said second conductivity type is an N-channel type.

Claim 16

A semiconductor integrated circuit device according to claim 11, wherein said first and second bipolar transistors are NPN bipolar transistors.

Claim 17

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said address circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said address circuit, and further wherein said reading means in said signal circuit includes differential bipolar transistors coupled to receive an output signal of said specified storage means.

Claim 18

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said address circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said address circuit, and further wherein said reading means in said signal circuit includes differential bipolar transistors coupled to receive an output signal of said specified storage means.

Claim 19

A semiconductor integrated circuit as defined in claim 13, wherein said address circuit further includes an address buffer to which address signals are applied, and wherein said bipolar output transistor comprises a bipolar output transistor of said address buffer which executes at least one of charge and discharge of a signal output line of said address buffer.

Claim 20

A semiconductor integrated circuit as defined in claim 13, wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the storage means, and wherein a plurality of said output bipolar transistors are provided to execute at least one of charge and discharge of said word lines.

Claim 21

A semiconductor integrated circuit according to claim 13, wherein said siganl circuit further includes means for writing information into said storage means, and wherein said timing circuit further includes means for controlling operations of writing information by said writing means.

Claim 22

A semiconductor integrated circuit as defined in claim 16, wherein said address circuit includes an address buffer to which address signals are applied, and wherein said bipolar output transistor comprises a bipolar output transistor of said address buffer which executes at least one of charge and discharge of a signal output line of said address buffer.

Claim 23

A semiconductor integrated circuit as defined in claim 16, wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the storage means, and wherein a plurality of said output bipolar transistors are provided to execute at least one of charge and discharge of said word lines.

Claim 24

A semiconductor integrated circuit according to claim 13, wherein said address circuit further includes a second bipolar output transistor which executes the other of charge and discharge of said signal output line of said at least one circuit in said address circuit.

Claim 25

A semiconductor integrated circuit as defined in claim 19, wherein said address circuit further includes an address buffer to which address signals are applied, and wherein said bipolar output transistors comprise bipolar output transistors of said address buffer which execute charge and discharge of a signal output line of said address buffer.

Claim 26

A semiconductor integrated circuit as defined in claim 19, wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the storage means, and wherein a plurality of said output bipolar transistors are provided to execute charge and discharge of said word lines.

Claim 27

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said timing circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said timing circuit, and further wherein said reading means in said signal circuit includes differential bipolar transistors coupled to receive an output signal of said specified storage means.

Claim 28

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said timing circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said timing circuit, and further wherein said reading means in said signal circuit includes differential bipolar transistors coupled to receive an output signal of said specified storage means.

Claim 29

A semiconductor integrated circuit as defined in claim 22, wherein said timing circuit includes an internal control signal generator circuit which is supplied with a chip select signal and a write enable signal, thereby to generate an internal delayed chip select signal and a write control signal.

Claim 30

A semiconductor integrated circuit according to claim 22, wherein said signal circuit further includes means for writing information into said storage means, and wherein said timing circuit further includes means for controlling operations of writing information by said writing means.

Claim 31

A semiconductor integrated circuit as defined in claim 24, wherein said timing circuit includes an internal control signal generator circuit which is supplied with a chip select signal and a write enable signal, thereby to generate an internal delayed chip select signal and a write control signal.

Claim 32

A semiconductor integrated circuit according to claim 22, wherein said timing circuit further includes a second bipolar output transistor which executes the other of charge and discharge of said signal output line of said at least one circuit in said timing circuit.

Claim 33

A semiconductor integrated circuit as defined in claim 26, wherein said timing circuit includes an internal control signal generator circuit which is supplied with a chip select signal and a write enable signal, thereby to generate an internal delayed chip select signal and a write control signal.

Claim 34

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said signal circuit includes a data output buffer for obtaining an information output signal at an external output terminal, said data output buffer including a principal portion constructed of a CMOS circuit, and at least one bipolar transistor, which executes at least one of charge and discharge of a gate capacitance of an output MISFET of said data output buffer, said output MISFET having a source-drain path coupled to said external output terminal.

Claim 35

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said signal circuit includes a data output buffer for obtaining an information output signal at an external output terminal, said data output buffer including a principal portion constructed of a CMOS circuit, and at least one bipolar transistor, which executes at least one of charge and discharge of a gate capacitance of an output MISFET of said data output buffer, said output MISFET having a source-drain path coupled to said external output terminal.

Claim 36

A semiconductor integrated circuit as defined in claim 28, wherein said output MISFET is controlled into an "off" state by a data output buffer control signal.

Claim 37

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said signal circuit includes a data output buffer for obtaining an information output signal at an external output terminal, said data output buffer including a principal portion constructed of a CMOS circuit, and a plurality of bipolar transistors, which execute charge and discharge of a gate capacitance of an output MISFET of said data output buffer, said output MISFET having a source-drain path coupled to said external output terminal.

Claim 38

A semiconductor integrated circuit comprising: a plurality of storage means for storing information therein; an address circuit for selecting a specified storage means from among said plurality of storage means; a signal circuit coupled to said storage means and including means for reading information from said storage means; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said signal circuit includes a data output buffer for obtaining an information output signal at an external output terminal, said data output buffer including a principal portion constructed of a CMOS circuit, and a plurality of bipolar transistors, which execute charge and discharge of a gate capacitance of an output MISFET of said data output buffer, said output MISFET having a source-drain path coupled to said external output terminal.

Claim 39

A semiconductor integrated circuit as defined in claim 30, wherein said output MISFET is controlled into an "off" state by a data output buffer control signal.

Claim 40

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for reading information from said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said address circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said address circuit, and wherein said address circuit further includes an address buffer to which address signals are applied, and wherein said bipolar output transistor comprises a bipolar output transistor of said address buffer which executes at least one of charge and discharge of a signal output line of said address buffer.

Claim 41

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for reading information from said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said address circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said address circuit, and wherein said address circuit further includes an address buffer to which address signals are applied, and wherein said bipolar output transistor comprises a bipolar output transistor of said address buffer which executes at least one of charge and discharge of a signal output line of said address buffer.

Claim 42

A semiconductor integrated circuit according to claim 32, wherein said address buffer further includes a second bipolar output transistor which executes the other of charge and discharge of said signal output line of said address buffer.

Claim 43

A semiconductor integrated circuit according to claim 33, wherein said signal circuit further includes means for writing information into said memory cells, and wherein said timing circuit further includes means for controlling operations of writing information by said writing means.

Claim 44

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for reading information from said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the memory cells, and wherein said row decoder includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of at least one of said word lines.

Claim 45

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for reading information from said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the memory cells, and wherein said row decoder includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of at least one of said word lines.

Claim 46

A semiconductor integrated circuit according to claim 35, wherein said row decoder further includes a second bipolar output transistor which executes the other of charge and discharge of said at least one of said word lines.

Claim 47

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cells from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for reading information from said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said timing circuit includes an internal control signal generator circuit which is supplied with a chip select signal, thereby to generate an internal delayed chip select signal, and wherein said internal control signal generator circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said internal control signal generator circuit.

Claim 48

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cells from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for reading information from said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading information, wherein said timing circuit includes an internal control signal generator circuit which is supplied with a chip select signal, thereby to generate an internal delayed chip select signal, and wherein said internal control signal generator circuit includes a principal portion constructed of a CMOS circuit, and at least one bipolar output transistor, which executes at least one of charge and discharge of a signal output line of at least one circuit in said internal control signal generator circuit.

Claim 49

A semiconductor integrated circuit according to claim 37, wherein said internal control signal generator further includes a second bipolar output transistor which executes the other of charge and discharge of said signal output line of said at least one circuit in said internal control signal generator circuit.

Claim 50

A semiconductor integrated circuit according to claim 38, wherein said signal circuit further includes means for writing information into said memory cells, wherein said timing circuit further includes means for controlling operations of writing information by said writing means, and wherein said internal control signal generator circuit is further supplied with a write enable signal, thereby to generate a write control signal.

Claim 51

A semiconductor integrated circuit comprising: an input node; first and second output nodes; first and second power supply terminals for supplying first and second power supply levels, respectively, to said semiconductor circuit; a first bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said first output node; a second bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said first output node; a first MOS transistor of a first conductivity type having a gate coupled to said input node; a second MOS transistor of a second conductivity type opposite to said first conductivity type having a gate coupled to said input node, wherein said first and second MOS transistors are coupled in series with one another to have their respective source-drain paths coupled in series between said first output node and said second power supply terminal to form a CMOS inverter circuit, and wherein a base of said second bipolar transistor is coupled to a junction between the respective source-drain paths of said first and second MOS transistors, and further wherein a base of said first bipolar transistor is coupled to said input node; a third bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said second output node; a fourth bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said second output node; a CMOS circuit having an input coupled to said input node and having first and second outputs coupled, respectively, to bases of said third and fourth bipolar transistors, wherein said CMOS circuit includes means for driving said third and fourth bipolar transistors in a push-pull mode of operation; and a discharge MOS transistor coupled to have a source-drain path coupled between a base of said fourth bipolar transistor and said second power supply terminal, said discharge MOS transistor also having a gate coupled to said first output of said CMOS circuit so that discharge of the base capacitance of said fourth bipolar transistor is controlled by said first output of said CMOS circuit which is coupled to the base of said third bipolar transistor, wherein said CMOS circuit includes a third MOS transistor of said first conductivity type having a gate coupled to said input node and having a source-drain path coupled between said first power supply terminal and said first output of said CMOS circuit, a fourth MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second power supply terminal and said first output of said CMOS circuit, and a fifth MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second output node and the second output of said CMOS circuit.

Claim 52

A semiconductor integrated circuit comprising: an input node; first and second output nodes; first and second power supply terminals for supplying first and second power supply levels, respectively, to said semiconductor circuit; a first bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said first output node; a second bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said first output node; a first MOS transistor of a first conductivity type having a gate coupled to said input node; a second MOS transistor of a second conductivity type opposite to said first conductivity type having a gate coupled to said input node, wherein said first and second MOS transistors are coupled in series with one another to have their respective source-drain paths coupled in series between said first output node and said second power supply terminal to form a CMOS inverter circuit, and wherein a base of said second bipolar transistor is coupled to a junction between the respective source-drain paths of said first and second MOS transistors, and further wherein a base of said first bipolar transistor is coupled to said input node; a third bipolar transistor having an emitter-collector path coupled between said first power supply terminal and said second output node; a fourth bipolar transistor having an emitter-collector path coupled between said second power supply terminal and said second output node; a CMOS circuit having an input coupled to said input node and having first and second outputs coupled, respectively, to bases of said third and fourth bipolar transistors, wherein said CMOS circuit includes means for driving said third and fourth bipolar transistors in a push-pull mode of operation; and a discharge MOS transistor coupled to have a source-drain path coupled between a base of said fourth bipolar transistor and said second power supply terminal, said discharge MOS transistor also having a gate coupled to said first output of said CMOS circuit so that discharge of the base capacitance of said fourth bipolar transistor is controlled by said first output of said CMOS circuit which is coupled to the base of said third bipolar transistor, wherein said CMOS circuit includes a third MOS transistor of said first conductivity type having a gate coupled to said input node and having a source-drain path coupled between said first power supply terminal and said first output of said CMOS circuit, a fourth MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second power supply terminal and said first output of said CMOS circuit, and a fifth MOS transistor of said second conductivity type having a gate coupled to said input node and having a source-drain path coupled between said second output node and the second output of said CMOS circuit.

Claim 53

A semiconductor integrated circuit device according to claim 40, wherein said discharge MOS transistor is of said second conductivity type.

Claim 54

A semiconductor integrated circuit device according to claim 41, wherein said first conductivity type is a P-channel type, and wherein said second conductivity type is an N-channel type.

Claim 55

A semiconductor integrated circuit device according to claim 42, wherein said first, second, third and fourth bipolar transistors are NPN bipolar transistors.

Claim 56

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a CMOS circuit, and bipolar output transistors which execute charge and discharge of a signal output line of at least one circuit in said address circuit, and wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the memory cells, and wherein a plurality of said output bipolar transistors are provided to execute charge and discharge of said word lines.

Claim 57

A semiconductor integrated circuit comprising: a plurality of memory cells; an address circuit for selecting a specified memory cell from among said plurality of memory cells; a signal circuit coupled to said memory cells and including means for respectively reading and writing information from and into said memory cells; and a timing circuit coupled to said signal circuit for controlling operations of reading and writing information, wherein said address circuit includes a principal portion constructed of a CMOS circuit, and bipolar output transistors which execute charge and discharge of a signal output line of at least one circuit in said address circuit, and wherein said address circuit includes a row decoder which executes charge and discharge of word lines of the memory cells, and wherein a plurality of said output bipolar transistors are provided to execute charge and discharge of said word lines.