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JPS598431A Expired / Lapsed JP ⏱️ 0.0 years remaining

Buffer circuit

Assignee: Hitachi Ltd
•
Filing: 1982-07-07
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Granted: —
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Expires: 2002-07-07
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Abstract

Abstract PURPOSE:To obtain a circuit of high speed and low power consumption by combining bipolar and CMOS transistors(TRs) to constitute a noninverting type composite buffer circuit. CONSTITUTION:N-channel MOSTRs QM1, QM2, P-channel MOSTRs QM2, QM3 and NPN bipolar TRs QB1, QB2 are provided. When both inputs and outputs are at high potential, the TR sQM2, QM3 are turned off and the TRs QM1, QM2 are turned on. Thus, the TRQB2 turns off and a load of an output OUT is capacitive, then the TRQM1 turns off. When the output OUT goes to a low potential, since no base current is applied from the output OUT to the TRQB2, the TRQB2 turns off and no current flows to the TRQB1. As far as the input/ output remains at high or low potentials, only the leakage current flows and the power consumption is almost zero.

Inventors

  • 👤 Noriyuki Honma
  • 👤 本間 紀之
  • 👤 Hisayuki Higuchi
  • 👤 樋口 久幸

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 19:02
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

US3609479A Cited
JPS5619660A Cited

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