US4924425A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for immediately writing an operand to a selected word location within a block of a buffer memory
Assignee: Fujitsu Ltd
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Filing: 1987-07-08
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Granted: 1990-05-08
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Expires: 2007-07-08
Abstract
Abstract A method for controlling a buffer memory for storing a copy of a portion of a main memory, including a step of detecting whether the address in question exists in the buffer memory in response to an instruction to carry out reading from and subsequent writing into the same address. In the case where the results of the detection are affirmative, reading of the data from the address in question and the subsequent writing of the result of a calculation into the address in question are carried out. In the case where the results of the detection are negative, an instruction for the main memory to read data in the block which contains the address in question is issued. The read data in the block is transferred from the main memory to the buffer memory, the transferred data is written into the buffer memory with the word of the requested address placed as the beginning word of the data, and the beginning word of the data from the buffer memory is picked-up. The picked-up beginning word is transmitted to a calculation portion, and the results of the calculation are written into the same address of the buffer memory in succession to the writing of the beginning word of the data.
Inventors
- 👤 Satoru Koga
- 👤 Tsutomu Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:56
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
239 words
A method for controlling a buffer memory in a data processing apparatus having a central processing unit which includes the buffer memory, the buffer memory storing a copy of a portion of a main memory, said method comprising the steps of: (a) detecting, first, a word unit of a block up to which writing in the buffer memory has been completed during a process of writing a plurality of word units constituting a block from the main memory into the buffer memory, the word units being written in sequence; (b) detecting, second, the existence of an address of block containing a write request word from the central processing unit, for writing of an operand in the block which is currently being written into the buffer memory from the main memory; and (c) detecting, third, the completion of writing of the word unit in the block which is being written into the buffer memory from the main memory, which corresponds to an address of the write request word from the central processing unit; wherein, when a result of said third detecting step indicates that the address of the word unit in the block corresponding to the address of the write request word from the central processing unit has already been written from the main memory into the buffer memory, writing of the operand into the buffer memory is executed even if the writing of the entire block is not completed.
Claim 2
Independent Claim
239 words
A method for controlling a buffer memory in a data processing apparatus having a central processing unit which includes the buffer memory, the buffer memory storing a copy of a portion of a main memory, said method comprising the steps of: (a) detecting, first, a word unit of a block up to which writing in the buffer memory has been completed during a process of writing a plurality of word units constituting a block from the main memory into the buffer memory, the word units being written in sequence; (b) detecting, second, the existence of an address of block containing a write request word from the central processing unit, for writing of an operand in the block which is currently being written into the buffer memory from the main memory; and (c) detecting, third, the completion of writing of the word unit in the block which is being written into the buffer memory from the main memory, which corresponds to an address of the write request word from the central processing unit; wherein, when a result of said third detecting step indicates that the address of the word unit in the block corresponding to the address of the write request word from the central processing unit has already been written from the main memory into the buffer memory, writing of the operand into the buffer memory is executed even if the writing of the entire block is not completed.
Claim 3
Dependent Claim
36 words
A method according to claim 1, wherein said first detecting step is carried out by using a partial validity flag register, and wherein said second and third detecting steps are carried out by using comparison circuits.
Claim 4
Independent Claim
217 words
A method for controlling a buffer memory in a data processing apparatus having a central processing unit which includes the buffer memory, the buffer memory storing a copy of a portion of a main memory, said method comprising the steps of: (a) holding an address of a block to be loaded, upon block-loading from the main memory to the buffer memory; (b) successively transferring a plurality of words constituting a block, word by word, to the buffer memory and designating a selected flag among partial validity flags arranged in correspondence with the words in the block at each transfer of one word, upon block-loading from the main memory to the buffer memory; (c) checking the coincidence between an address of block containing a write request word and the address of the block under load operation held in said holding step (a); (d) checking whether or not the transfer of the write request word is completed with reference to the flag designated in said transferring and designating step (b), when the result of said coincidence checking step (c) indicates a coincidence; and (e) when the result of said transfer completion checking step (d) indicates a completion, executing a writing into the buffer memory even if the transfer of the entire block which is being transferred is not completed.
Claim 5
Independent Claim
217 words
A method for controlling a buffer memory in a data processing apparatus having a central processing unit which includes the buffer memory, the buffer memory storing a copy of a portion of a main memory, said method comprising the steps of: (a) holding an address of a block to be loaded, upon block-loading from the main memory to the buffer memory; (b) successively transferring a plurality of words constituting a block, word by word, to the buffer memory and designating a selected flag among partial validity flags arranged in correspondence with the words in the block at each transfer of one word, upon block-loading from the main memory to the buffer memory; (c) checking the coincidence between an address of block containing a write request word and the address of the block under load operation held in said holding step (a); (d) checking whether or not the transfer of the write request word is completed with reference to the flag designated in said transferring and designating step (b), when the result of said coincidence checking step (c) indicates a coincidence; and (e) when the result of said transfer completion checking step (d) indicates a completion, executing a writing into the buffer memory even if the transfer of the entire block which is being transferred is not completed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-05-07 | 1993-11-06 | 1994-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-05-07 | 1997-11-06 | 1998-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-05-07 | 2001-11-06 | 2002-05-08 | $7700.00 | Window Closed / Lapsed |