US4616341A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Directory memory system having simultaneous write and comparison data bypass capabilities
Assignee: International Business Machines Corp
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Filing: 1983-06-30
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Granted: 1986-10-07
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Expires: 2003-06-30
Abstract
Abstract A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.
Inventors
- 👤 John E. Andersen
- 👤 Joseph A. Petrosky
- 👤 Benedicto U. Messina
- 👤 William D. Silkman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 14:19
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F16/00; G06F16/90; G06F16/901; G06F16/9017; G06F7/00; G06F7/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
117 words
A directory memory system having simultaneous writing and comparison data bypass capabilities, comprising: a memory block arranged in a plurality of arrays; byte select means responsive to each said array, for selectively coupling the output of one said arrays to a byte select output; compare logic receiving said outputs of each of said arrays and comparison data, for comparing said array outputs with said comparison data and for directing a comparison output to a first output data bus; means for coupling a selected one of (a) a data byte on said byte select output or (b) said comparison data, to a second output data bus; and selecting means for supplying a selection signal to said coupling means.
Claim 2
Dependent Claim
117 words
A directory memory system having simultaneous writing and comparison data bypass capabilities, comprising: a memory block arranged in a plurality of arrays; byte select means responsive to each said array, for selectively coupling the output of one said arrays to a byte select output; compare logic receiving said outputs of each of said arrays and comparison data, for comparing said array outputs with said comparison data and for directing a comparison output to a first output data bus; means for coupling a selected one of (a) a data byte on said byte select output or (b) said comparison data, to a second output data bus; and selecting means for supplying a selection signal to said coupling means.
Claim 3
Dependent Claim
129 words
The directory memory system of claim 1, wherein said coupling means comprises, for each bit of said output data bus: a first differential amplifier controlled by a respective bit of said output of said reading means; a second differential amplifier controlled by a respective bit of said comparison data, said first and second differential amplifiers each having complementary outputs coupled to a single set of first and second nodes; a current source; first and second current switch transistors for selectively coupling said current source to one of said first and second differential amplifiers for supplying operating current thereto; and wherein said selecting means comprises means for activating a selected one of said first and second current switch transistors for correspondingly activating one of said first and second differential amplifiers.
Claim 4
Dependent Claim
46 words
The directory memory system of claim 2, further comprising a push-pull amplifier stage for amplifying and buffering a signal produced differentially across said first and second nodes, an output of said push-pull amplifier stage being applied to a corresponding bit line of said output data bus.
Claim 5
Dependent Claim
65 words
The directory memory system of claim 3, wherein said means for activating said selected one of said first and second differential amplifiers comprises a third differential amplifier having an input receiving a bypass control signal; and first and second emitter-follower buffer transistors electrically connected to outputs of said third differential amplifier and to bases of respective ones of said first and second current switch transistors.
Claim 6
Dependent Claim
29 words
The directory memory system of claim 4, wherein a single one of said selecting means is provided for a plurality of each of said first and second differential amplifiers.
Claim 7
Dependent Claim
52 words
The directory memory system of claim 4, further comprising first and second voltage divider circuits coupled to emitters of said first and second emitter-follower buffer transistors, respectively, voltage division points of said first and second voltage divider circuits being connected to said bases of said first and second current switch transistors, respectively.
Claim 8
Dependent Claim
34 words
The directory memory system of claim 6, further comprising a fourth differential amplifier circuit for supplying differential control signals to said second differential amplifier in accordance with said respective bit of said comparison data.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-10-06 | 1990-04-07 | 1990-10-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-10-06 | 1994-04-07 | 1994-10-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-10-06 | 1998-04-07 | 1998-10-07 | $7700.00 | Window Closed / Lapsed |