US4922485A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for changing priority of packets of data
Assignee: L'ETAT FRANCAIS
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Filing: 1988-06-24
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Granted: 1990-05-01
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Expires: 2008-06-24
Abstract
Abstract A system for switching information packets assigned with two levels of semantic priorities between entering time muliplex lines and outgoing time multiplex lines, the read address of a packet in a buffer memory of a switch being stored in a queueing file associated with an outgoing port intended to transmit the packet. The read address is accompanied by a bit which defines the priority level of the packet. Each queueing file is comprised of two zones in series between the input and the output. Means is included for writing in the first zone only when the second zone is full, the first zone is accessible only to high priority level packets between the reading of files. The rear addresses of low priority level packets, which were stored earlier than the read address of high priority level packet the oldest still being present in the file, is overwritten in equal number, at a maximum, to the number of read addresses stored in the first zone.
Inventors
- 👤 Jean-Paul Quinquis
- 👤 Michel Servel
- 👤 Joel Francois
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 10:20
CPC Classifications
H; H04; H04L; H04L49/00; H04L49/10; H04L49/103; H04L49/20; H04L49/205; H04L49/25; H04L49/253; H04L49/254; H04L49/30
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
191 words
A system for switching information packets having two assigned levels of semantic priorities, said system comprising entering time multiplex lines, outgoing time multiplex lines, information packet switching means coupled between said entering and outgoing lines, a queueing file associated with each outgoing line, buffer memory means for storing a read address of a packet in said queueing file associated with an outgoing line which is to be used to transmit the packet, the read address being accompanied by a bit which defines a priority level of the packet, each of said queueing files comprising two zones coupled in series between an input and an output, means for writing only high priority level packets into the first zone only when the second zone is full, said writing occurring between the readings of said queueing files, and means for overwriting the read addresses of low priority level packets which were stored earlier than the oldest read address of high priority level packets which are present in the queueing file, the number of low priority packets being overwritten being equal, at a maximum, to the number of read addresses stored in the first zone.
Claim 2
Independent Claim
191 words
A system for switching information packets having two assigned levels of semantic priorities, said system comprising entering time multiplex lines, outgoing time multiplex lines, information packet switching means coupled between said entering and outgoing lines, a queueing file associated with each outgoing line, buffer memory means for storing a read address of a packet in said queueing file associated with an outgoing line which is to be used to transmit the packet, the read address being accompanied by a bit which defines a priority level of the packet, each of said queueing files comprising two zones coupled in series between an input and an output, means for writing only high priority level packets into the first zone only when the second zone is full, said writing occurring between the readings of said queueing files, and means for overwriting the read addresses of low priority level packets which were stored earlier than the oldest read address of high priority level packets which are present in the queueing file, the number of low priority packets being overwritten being equal, at a maximum, to the number of read addresses stored in the first zone.
Claim 3
Dependent Claim
84 words
A system in accordance with claim 1, and means for shifting said queueing file responsive to an overflow of a zone in the queueing file, with M read addresses in the first zone and more than M low priority level packet addresses between a read address which is present at an output of the queueing file and the oldest high priority level packet address present in the second zone after the read time of the file concerned, the shifting occurring at subsequent byte times.
Claim 4
Dependent Claim
121 words
A system in accordance with claim 1 and means for shifting the queueing responsive to a filling to an overflow of the second zone, with M read addresses in the first zone and less than M low priority level packet read addresses between a present address which is present at an output of the file queueing file and the oldest high level priority packet read address contained in the second zone, said shifting occurring after the read time of the file concerned, the file being subjected to a sufficient shift so that the high priority level packet read address is present at the output of the file, the shifts being done sequentially at the byte time rate after each reading time.
Claim 5
Independent Claim
189 words
A system in accordance with one of the claims 1, 2, or 3 and a plurality of processing circuits, each queueing file being associated with a processing circuit and having a data input for receiving an address word and a priority level bit, said priority bit being "1" for a low priority level and "0" for a high priority level, a write enable input, a write clocking input, a data output means for generating an address word and a priority bit, a shift enable input, a read clock input, an output signal for indicating that the second zone if full and an output indicating that the first zone is not empty, each of said processing circuits comprising a first AND gate, one input of which receives the selection signal enabling writing in the file and a second input of which is connected to an output of a NAND gate, one input of which receives the priority bit and another input of which is connected to the output for indicating that the second zone if full, and an output of the first AND gate connected to the write enable input.
Claim 6
Dependent Claim
156 words
A system in accordance with claim 4 in which each of the processing circuits comprises a memory circuit, an OR gate, one input of which is enabled at each read time of the queueing file and a second input of which is connected to an output of a second AND gate, one input of said second AND gate receiving the priority bit present at the output of the queueing file and another input of which is connected to an output of said memory circuit having an input which is connected to the output indicating that the first zone is not empty, said memory circuit having a zero reset input which is enabled when an output indicating that the first zone is not empty is disabled and when the priority bit present at an output of the queueing file is at "0", and means for delaying a reset to zero by a period having one byte duration.
Claim 7
Independent Claim
78 words
A system in accordance with one of the claims 1, 2, or 3 and means for assigning of one of the two priority levels to each packet at the same time that an input label is converted to an output label and a selection is made of one or many queueing files into which the read address of the packet is stored, the bit defining the priority level being supplied by means for carrying out a set conversion.
Claim 8
Dependent Claim
31 words
A system in accordance with claim 6, in which the conversion means supplying a priority level bit is common to all queueing files in which the packet read address is stored.
Claim 9
Dependent Claim
44 words
A system in accordance with claim 6, in which the conversion means selectively supplies the high priority level bit to some of the queueing files in which the packet read address is stored and supplies the low level priority to the others queueing files.
Claim 10
Dependent Claim
49 words
A system in accordance with claim 6, and means associated with said conversion means for loading control information concerning the conversion, selecting the queueing files, and assigning the priority levels is carried out in the conversion means at the time when said packet switching means is being set up.
Claim 11
Dependent Claim
63 words
A system in accordance with claim 4, in which one of the two priority levels is assigned to each packet at the same time that a input label conversion is made to an output label, and one or many queueing files is selected for storing a read address of the packet, the bit defining the priority level being supplied by the conversion means.
Claim 12
Dependent Claim
63 words
A system in accordance with claim 5, in which one of the two priority levels is assigned to each packet at the same time that there is a label conversion to an output label and that one or many queueing files are selected to store the read address of the packet, the bit defining the priority level being supplied by the conversion means.
Claim 13
Dependent Claim
31 words
A system in accordance with claim 10, in which the conversion means supplies a priority level bit in common to all queueing files in which the packet read address is stored.
Claim 14
Dependent Claim
31 words
A system in accordance with claim 11, in which the conversion means supplies a priority level bit in common to all queueing files in which the packet read address is stored.
Claim 15
Dependent Claim
42 words
A system in accordance with claim 10, in which the conversion means selectively supplies the high priority level bit to some of the queueing files in which the packet read address is stored, and supplies the low level priority to the others.
Claim 16
Dependent Claim
42 words
A system in accordance with claim 11, in which the conversion means selectively supplies the high priority level bit to some of the queueing files in which the packet read address is stored, and supplies the low level priority to the others.
Claim 17
Dependent Claim
35 words
A system in accordance with claim 7, in which the conversion means load control information concerning the conversion, selects the queueing files, and assigns the priority levels at the time of setting up a link.
Claim 18
Dependent Claim
36 words
A system in accordance with claim 8, in which the conversion means load control information concerning the conversions, selects the queueing files, and the assigns the priority levels at the time of setting up a link.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |