Packet switch trunk circuit queueing arrangement

Claim 2

A data packet sorter for interfacing a received multichannel packet data stream to a communication line, said sorter comprising means for sorting received multichannel data packets equal to or greater than a predetermined size for storage in a first memory and for sorting multichannel data packets less than said predetermined size for storage in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; and counter means including a channel counter associated with each channel of the received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrementing the associated channel counter for each data packet read from said first memory.

Claim 3

The data packet sorter of claim 1 wherein said sorting means includes means for storing said multichannel data packets less than said predetermined size in a second memory in response to a zero count signal from the associated channel counter.

Claim 4

The data packet sorter of claim 2 wherein said counter means further counts all data packets written into said second memory and decrements when each data packet is read from said second memory.

Claim 5

A trunk circuit for interfacing a received multichannel packet data stream to a communication trunk, said trunk circuit comprising a first memory; a second memory; means for sorting multichannel data packets equal to or greater than a predetermined size for storage in said first memory and for sorting multichannel data packets less than said predetermined size in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; means for storing said multichannel data packets less than said predetermined side in said second memory in response to a zero count signal from the associated channel counter; counter means including a channel counter associated with each channel of said received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrmenting the associated channel counter for each data packet read from said first memory; and means for reading a data packet from said first memory only after having first read all of the data packets from said second memory.

Claim 6

A trunk circuit for interfacing a received multichannel packet data stream to a communication trunk, said trunk circuit comprising a first memory; a second memory; means for sorting multichannel data packets equal to or greater than a predetermined size for storage in said first memory and for sorting multichannel data packets less than said predetermined size in said first memory in response to a signal from an associated channel counter indicating that the count is not zero; means for storing said multichannel data packets less than said predetermined side in said second memory in response to a zero count signal from the associated channel counter; counter means including a channel counter associated with each channel of said received multichannel packet data stream for counting, for each channel, the number of data packets written into said first memory by incrementing said associated channel counter for each data packet written into said first memory and decrmenting the associated channel counter for each data packet read from said first memory; and means for reading a data packet from said first memory only after having first read all of the data packets from said second memory.

Claim 7

The trunk circuit of claim 4 further comprising a framing means for grouping data packets read from said first and said second memories into a data frame for output to said communication trunk.

Claim 8

The trunk circuit of claim 4 wherein said framing means further includes means for setting the frame length at a first predetermined number of data bytes when the data includes only data packets from said second memory and for setting the frame length at a second predetermined number of data bytes when the data includes data packets from both said first and second memories.

Claim 9

The trunk circuit of claim 4 wherein said second memory generates a full memory signal and wherein said sorting means is responsive to said full memory signal for storing all data packets in said first memory.

Claim 10

The trunk circuit of claim 4 wherein said first memory generates a high water mark signal indicating that said first memory is almost full and wherein said sorting means is responsive to said high water mark signal and a zero count signal from the channel counter means associated with a received data packet for inhibiting the writing of the received data packet into said first memory.

Claim 11

The trunk circuit of claim 4 wherein said associated channel counter means generates a full count signal when the number of data packets stored in said first memory for a channel exceeds a predetermined limit and wherein said sorting means is responsive to said full count signal for disabling the writing of any data packets from the full channel into said first memory.

Claim 14

The method of sorting of claim 10 wherein said sorting step includes the steps of: writing said data packets less than said predetermined size in a second memory when the associated channel counter is zero.