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US4922445A
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Logic circuit simulation method
Assignee: Hitachi Ltd
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Filing: 1987-12-04
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Granted: 1990-05-01
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Expires: 2007-12-04
Abstract
Abstract A logic circuit simulation method for simulating a logic circuit including a plurality of logic blocks, in which after having simulated the whole simulation object logic circuit, signal variation information of an arbitrary logic block is taken out from the simulation result, the information thus taken out is given to the logic blocks, and a renewed simulation is executed for every logic block.
Inventors
- 👤 Yoshito Mizoue
- 👤 Yoshiharu Kazama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:21
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
146 words
A logic circuit simulation method for simulating a logic circuit including a plurality of interconnected logic blocks, comprising the steps of: simulating operation of said logic circuit including said plurality of interconnected logic blocks, outputting connection information of connections between said logic blocks and signal variation information occurring on said connections between said logic blocks at different simulation times and storing said information in an output result file; and extracting only signal variation information, related to a specific erroneously operating logic block to be resimulated, from said signal variation information stored in said output resut file and resimulating said logic circuit by simulating operation of each of said logic blocks relative to said specific erroneously operating logic block to be resimulated using said extracted signal variation information at each simulation time as an input signal source to said specific erroneously operating logic block to be resimulated.
Claim 2
Dependent Claim
146 words
A logic circuit simulation method for simulating a logic circuit including a plurality of interconnected logic blocks, comprising the steps of: simulating operation of said logic circuit including said plurality of interconnected logic blocks, outputting connection information of connections between said logic blocks and signal variation information occurring on said connections between said logic blocks at different simulation times and storing said information in an output result file; and extracting only signal variation information, related to a specific erroneously operating logic block to be resimulated, from said signal variation information stored in said output resut file and resimulating said logic circuit by simulating operation of each of said logic blocks relative to said specific erroneously operating logic block to be resimulated using said extracted signal variation information at each simulation time as an input signal source to said specific erroneously operating logic block to be resimulated.
Claim 3
Dependent Claim
39 words
A logic circuit simulation method according to claim 1, wherein said signal variation information is outputted to and stored in the output result file in correspondence to input/output signal lines of said connections interconnecting each of the logic blocks.
Claim 4
Dependent Claim
82 words
A logic circuit simulation method according to claim 1, wherein said extracted signal variation information corresponds to input terminals of each of the logic blocks and signal values of said signal variation information whose simulation time at the time of the resimulation and whose simulation time at the time of outputting said information for storage in said output result file being coincident with each other is supplied to the input terminals of each of the logic blocks and the input signal source.
Claim 5
Dependent Claim
17 words
A logic circuit simulation method according to claim 1, wherein a unit of logic blocks is LSI.
Claim 6
Dependent Claim
17 words
A logic circuit simulation method according to claim 2, wherein a unit of logic blocks is LSI.
Claim 7
Dependent Claim
17 words
A logic circuit simulation method according to claim 3, wherein a unit of logic blocks is LSI.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-30 | 1993-10-30 | 1994-05-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-30 | 1997-10-30 | 1998-05-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-30 | 2001-10-30 | 2002-05-01 | $7700.00 | Window Closed / Lapsed |