Scan circuit using a plural bootstrap effect for forming scan pulses

Claim 2

A scan circuit comprising a plurality of stages of interconnected unit circuits, in which scan pulses are sequentially output from said unit circuits in response to drive pulses; a first one of said unit circuits including a first input terminal, a first output terminal and first bootstrap means, and a second one of said unit circuits including a second input terminal, a second output terminal and second bootstrap means; wherein a first potential at said first output terminal is raised by said first bootstrap means when a drive pulse is input to said first input terminal of said first unit circuit, said first output terminal of said first unit circuit being connected to said second input terminal of said second unit circuit so as to apply said first potential thereto; and wherein the raised first potential at the first output terminal is further raised by raising a second potential at said second output terminal of said second unit circuit by said second bootstrap means in response to a further drive pulse, the further raised first potential being output as one of said scan pulses.

Claim 3

A scan circuit according to claim 1, wherein each said unit circuit has a plurality of transistors.

Claim 4

A scan circuit according to claim 2, wherein said unit circuits respectively have input terminals and each of said unit circuits has a first transistor whose gate is connected to said input terminal.

Claim 5

A scan circuit according to claim 3, wherein a capacitor is connected between the gate and source of said first transistor.

Claim 6

A scan circuit according to claim 3, wherein the first unit circuit is at a front stage and the second unit circuit is at a next stage connected thereto.

Claim 7

A scan circuit comprising a plurality of stages of interconnected unit circuits, said unit circuits being used in a shift register, a unit circuit of each stage comprising: an input terminal; a first field effect transistor whose gate electrode is connected to said input terminal of said unit circuit; a capacitor connected between said gate electrode and a source electrode of said first transistor; a first signal source connected to a drain electrode of said first transistor; a second field effect transistor whose drain electrode is connected to said source electrode of the first transistor, a source electrode of said second transistor being connected to ground and a gate electrode of said second transistor being connected to a second signal source; a third field effect transistor whose gate electrode and drain electrode are connected to said source electrode of the first transistor, a source electrode of said third transistor being connected to a drain electrode of fourth field effect transistor of a unit circuit of a stage preceding the stage of said unit circuit, a source electrode of the fourth transistor being connected to ground and a gate electrode of the fourth transistor being connected to a third signal source; and a signal output terminal for outputting a signal at the gate electrode of said first transistor to the outside of the shift register, said signal at said signal output terminal being applied to a drain electrode of the fourth transistor.

Claim 8

A scan circuit comprising a plurality of stages of interconnected unit circuits, said unit circuits being used in a shift register, a unit circuit of each stage comprising: an input terminal; a first field effect transistor whose gate electrode is connected to said input terminal of said unit circuit; a capacitor connected between said gate electrode and a source electrode of said first transistor; a first signal source connected to a drain electrode of said first transistor; a second field effect transistor whose drain electrode is connected to said source electrode of the first transistor, a source electrode of said second transistor being connected to ground and a gate electrode of said second transistor being connected to a second signal source; a third field effect transistor whose gate electrode and drain electrode are connected to said source electrode of the first transistor, a source electrode of said third transistor being connected to a drain electrode of fourth field effect transistor of a unit circuit of a stage preceding the stage of said unit circuit, a source electrode of the fourth transistor being connected to ground and a gate electrode of the fourth transistor being connected to a third signal source; and a signal output terminal for outputting a signal at the gate electrode of said first transistor to the outside of the shift register, said signal at said signal output terminal being applied to a drain electrode of the fourth transistor.

Claim 9

A scan circuit comprising: at least two bootstrap means for raising potentials of respective drive pulses; and an output terminal connected at an interconnection point between said two bootstrap means; wherein a scan pulse is provided at said output terminal by adding the drive pulses whose potentials are respectively raised by said bootstrap means.

Claim 10

A scan circuit comprising: at least two bootstrap means for raising potentials of respective drive pulses; and an output terminal connected at an interconnection point between said two bootstrap means; wherein a scan pulse is provided at said output terminal by adding the drive pulses whose potentials are respectively raised by said bootstrap means.

Claim 11

A scan circuit according to claim 7, wherein each of said bootstrap means includes a capacitor.

Claim 12

A scan circuit according to claim 7, wherein each of said bootstrap means is disposed in a unit circuit including a plurality of transistors.

Claim 13

A scan circuit according to claim 9, wherein each of said unit circuits has an input terminal and a first field effect transistor whose gate electrode is connected to the respective input terminal.

Claim 14

A scan circuit according to claim 10, wherein a capacitor is provided between the gate electrode and a source electrode of said first transistor.

Claim 15

A scan circuit according to claim 11, wherein said output terminal is at a front stage and is connected to the input terminal of the unit circuit at a next stage.

Claim 16

A scan circuit comprising: at least two bootstrap means for raising potentials of respective drive pulses; an output terminal connected at an interconnection point between said two bootstrap means; and switching means connected between one of said two bootstrap means and said output terminal; wherein a potential of one of said drive pulses is raised by said one bootstrap means and said switching means is thereby opened, and wherein a potential of the other drive pulse is raised by the other bootstrap means and said switching means is thereby closed, thereby providing a scan pulse at said output terminal.

Claim 17

A scan circuit comprising: at least two bootstrap means for raising potentials of respective drive pulses; an output terminal connected at an interconnection point between said two bootstrap means; and switching means connected between one of said two bootstrap means and said output terminal; wherein a potential of one of said drive pulses is raised by said one bootstrap means and said switching means is thereby opened, and wherein a potential of the other drive pulse is raised by the other bootstrap means and said switching means is thereby closed, thereby providing a scan pulse at said output terminal.

Claim 18

A scan circuit according to claim 13, wherein said switching means includes a transistor.

Claim 19

A scan circuit according to claim 13, wherein each of said bootstrap means includes a capacitor.

Claim 20

A scan circuit according to claim 13, wherein each of said strap means is connected in a respective unit circuit including a plurality of transistors.

Claim 21

A scan circuit according to claim 16, wherein each of said unit circuits has an input terminal and a first field effect transistor whose gate electrode is connected to the respective input terminal.

Claim 22

A scan circuit according to claim 17, wherein a capacitor is connected between the gate electrode and a source electrode of said first transistor.

Claim 23

A scan circuit according to claim 18, wherein said output terminal is at a front stage and is connected to the input terminal of a unit circuit at a next stage.