Scanning pulse generator

Claim 2

In a sequential scanning pulse generator comprising a pulse source for providing drive pulses, a shift register means including a plurality of unit circuits connected in cascade, each of said drive pulses being fed to the first stage of said cascade connection of the unit circuits and delayed for a predetermined time thereby and means for deriving the delayed pulses from said unit circuits, the improvement comprising a circuit provided for each of said unit circuits to divide a delayed pulse therefrom into a plurality of sequential pulses and means for deriving the divided sequential pulses from the pulse dividing circuit.

Claim 3

The sequential scanning pulse generator according to claim 1, in which said each pulse dividing circuit comprises input means for receiving a delayed pulse from its associated unit circuit of said shift register means, a plurality of transistor elements with which said input means is connected coupled and output means provides for each of said transistor elements, and means for generating trains of clock pulses is connected with each of said transistors elements, said trains of clock pulses being of different phases and applied to said different transistor elements in synchronism with said delayed pulses from said input means, the arrangement being such that said transistor elements are made operative not simultaneously but in conformity with the different phase of said trains of clock pulses.

Claim 4

The sequential scanning pulse generator according to claim 2, in which said transistor elements are insulated gate field-effect transistors.

Claim 5

The sequential scanning pulse generator according to claim 3, in which each said pulse dividing circuit has the drain of each of said transistors supplied with a different one of said trains of clock pulses, the gates of all of said transistors connected in common with said input means, and the sources of said transistors connected with their corresponding output means.

Claim 6

The sequential scanning pulse generator according to claim 3, in which each said pulse dividing circuit has the drains of all of said transistors connected in common with said input means, the gate of each of said transistors supplied with a different one of said trains of clock pulses, and the sources of said transistors connected with their corresponding output means.

Claim 7

The sequential scanning pulse generator according to claim 3, in which each of said pulse dividing circuit includes: an input terminal connected with its associated unit circuit of said shift register means; first, second, third and fourth clock terminals; first and fifth transistors having their gates connected in common with said first clock terminal and their drains connected in common with said input terminal; third and seventh transistors having their gates connected in cOmmon with said second clock terminal and their drains connected in common with said input terminals; second and fourth transistors having their gates connected in common with said third clock terminal, the drains of said second and fourth transistors being connected with the sources of said first and third transistors respectively; sixth and eighth transistors having their gates connected in common with said fourth clock terminal, the drains of said sixth and eighth transistors being connected with the sources of said fifth and seventh transistors respectively; and first, second, third and fourth output terminals connected with the sources of said second, fourth, sixth and eighth transistors respectively; and in which said clock pulse train generating circuit supplies said first and second clock terminals with first and second trains of clock pulses of the same pulse width of opposite polarities with each other and supplies said third and fourth clock terminals with third and fourth trains of clock pulses having the same pulse width identical with twice the pulse width of said first and second pulse trains and opposite polarities with each other.