Frame synchronizing apparatus

Claim 2

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals including serial signals at a rate of f 0 bits per second (bps), said serial signals including a frame synchronizing signal with n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching said parallel signals in response to a latch timing pulse; synchronization detecting means for detecting said frame synchronizing signal from said parallel signals; latch timing signal generating means for generating said latch timing pulse at a rate of f 0 /k (bps) where 1<k<n, so that said latching means latches said parallel signals a plurality of times while receiving a frame of said digital signals; and phase shifting means for changing the rate of said latch timing pulse in response to said synchronization detecting means not detecting said frame synchronizing signal while receiving said frame.

Claim 3

A frame synchronizing apparatus as set forth in claim 1, wherein said synchronization detecting means a predetermined number smaller than n of a synchronization detecting circuits connected to detect said frame synchronizing signal by extracting said parallel signals latched respectively in different positions in said latching means.

Claim 4

A frame synchronizing apparatus as set forth in claim 1, wherein said synchronization detecting means comprises: a predetermined number equal to n of a synchronization detecting circuits connected to detect said frame synchronizing signal by extracting said parallel signals latched respectively in different positions in said latching means.

Claim 5

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals including serial signals at a rate of f 0 bits per second (bps), said serial signals including a frame synchronizing signal with n bits or a part of the frame synchronizing signal collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching said parallel signals in response to a latch timing pulse; synchronization detecting means for detecting said frame synchronizing signal from said parallel signals; and latch timing signal generating means for providing said latch timing pulse having a frequency of f 0 /k Hz, where n>k≧2, before the detection of said frame synchronizing signal and having a frequency of f 0 /n Hz after the detection of said frame synchronizing signal.

Claim 6

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals including serial signals at a rate of f 0 bits per second (bps), said serial signals including a frame synchronizing signal with n bits or a part of the frame synchronizing signal collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching said parallel signals in response to a latch timing pulse; synchronization detecting means for detecting said frame synchronizing signal from said parallel signals; and latch timing signal generating means for providing said latch timing pulse having a frequency of f 0 /k Hz, where n>k≧2, before the detection of said frame synchronizing signal and having a frequency of f 0 /n Hz after the detection of said frame synchronizing signal.

Claim 7

A frame synchronizing apparatus as set forth in claim 4, wherein said latch timing signal generating means comprises a variable output counter for varying the frequency of said latch timing pulse (f 0 /k, f 0 /n) in accordance with a detection by said synchronization detecting means of a synchronization signal.

Claim 8

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals comprising serial signals at a rate of f 0 (bps), said serial signals including a frame synchronizing signal comprising n bits or a part of the same synchronizing signal collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching said parallel signals; parallel synchronization detecting means, having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of said latched signal to detect said frame synchronizing signal, comprising: plural stages of synchronization detecting portions; a synchronization control portion; and a synchronization protection portion; and latch timing signal generating means for providing, for said latching means, a latch timing pulse having a frequency of f 0 /k Hz, where n>k≧2, before the detection of said frame synchronizing signal and having a frequency of f 0 /n Hz after the detection of said frame synchronizing signal, said latch timing signal generating means comprising a variable output counter for varying the frequency of said latch timing pulse in accordance with a detection of a synchronization by said synchronization detecting means; whereby when a synchronization is detected in one of the outputs of said plural stages of synchronous detecting portion, said synchronization protection portion outputs a mode selecting signal for selecting the mode of said variable output counter.

Claim 9

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals comprising serial signals at a rate of f 0 (bps), said serial signals including a frame synchronizing signal comprising n bits or a part of the same synchronizing signal collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching said parallel signals; parallel synchronization detecting means, having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of said latched signal to detect said frame synchronizing signal, comprising: plural stages of synchronization detecting portions; a synchronization control portion; and a synchronization protection portion; and latch timing signal generating means for providing, for said latching means, a latch timing pulse having a frequency of f 0 /k Hz, where n>k≧2, before the detection of said frame synchronizing signal and having a frequency of f 0 /n Hz after the detection of said frame synchronizing signal, said latch timing signal generating means comprising a variable output counter for varying the frequency of said latch timing pulse in accordance with a detection of a synchronization by said synchronization detecting means; whereby when a synchronization is detected in one of the outputs of said plural stages of synchronous detecting portion, said synchronization protection portion outputs a mode selecting signal for selecting the mode of said variable output counter.

Claim 10

A frame synchronizing apparatus as set forth in claim 6, further comprising: output selection means for extracting from said latched signals, a signal of one time slot at a position corresponding to the synchronization detecting portion which has detected said frame synchronizing signal and outputting said extracted signal.

Claim 11

A frame synchronizing apparatus as set forth in claim 7, wherein said output selection means is a selector means for selecting a signal in one time slot from a plurality of output lines of said latching means under the control of the synchronization detecting portion which has detected said frame synchronizing signal.

Claim 12

A frame synchronizing apparatus as set forth in claim 7, wherein said output selection means is a phase selection means for changing the phase of a latch timing pulse in said latch timing signal generating means (103) under the control of the synchronization detecting portion which has detected said frame synchronous signal.

Claim 13

A frame synchronizing apparatus as set forth in claim 6, wherein said variable output counter comprises: a counter for generating two types of clocks (f 0 /k and f 0 /n) counters, phase selecting means for selecting one of k clocks output from one of said two counters for generating a timing of a unit of said frame, and a memory for storing the number of said synchronization detecting portion when said synchronization detecting portion detects a synchronization, whereby, the phase of the timing (f 0 /n) is changed by the stored number.

Claim 14

A synchronization apparatus as set forth in claim 6, further comprising a synchronization control portion for changing the clock (f 0 /n) from said variable output counter.

Claim 15

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals comprising serial signals at a rate of f 0 (bps), said serial signals including a frame synchronizing signal comprising n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching (2n-1) bits of said parallel signals; parallel synchronization detecting means, having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of latched (2n-1) bits to detect said frame synchronizing signal, comprising: (2n-1) stages of synchronization detecting portions; a synchronization control portion; and a synchronization protection portion; and output selection means for extracting, from said latched (2n-1) bits, a signal of one time slot at a position corresponding to the synchronization detecting portion which has detected said frame synchronizing signal and outputting said extracted signal; whereby a synchronization is detected in one of the outputs of said plural (2n-1) stages of synchronization detecting portions.

Claim 16

A frame synchronizing apparatus in a receiving apparatus for receiving digital signals for PCM communication, said digital signals comprising serial signals at a rate of f 0 (bps), said serial signals including a frame synchronizing signal comprising n bits or a part of the frame synchronizing signal, collectively arranged in one frame, said frame synchronizing apparatus comprising: latching means for converting said serial signals into parallel signals and for latching (2n-1) bits of said parallel signals; parallel synchronization detecting means, having a plurality of synchronization detecting portions each picking up different n bits from a one-bit-shifted position of latched (2n-1) bits to detect said frame synchronizing signal, comprising: (2n-1) stages of synchronization detecting portions; a synchronization control portion; and a synchronization protection portion; and output selection means for extracting, from said latched (2n-1) bits, a signal of one time slot at a position corresponding to the synchronization detecting portion which has detected said frame synchronizing signal and outputting said extracted signal; whereby a synchronization is detected in one of the outputs of said plural (2n-1) stages of synchronization detecting portions.

Claim 17

A frame synchronizing apparatus as set forth in claim 12, wherein said output selection means is selector means for selecting a signal in one time slot out of a plurality of output lines of said latching means under the control of the synchronization detecting portion which has detected said frame synchronizing signal.

Claim 18

A frame synchronizing apparatus as set forth in claim 12, wherein said output selection means (104B) is clock phase selection means for changing latch timing in said latching means (101B) under the control of the synchronization detecting portion which has detected said frame synchronous signal.

Claim 19

A frame synchronizing apparatus as set forth in claim 12, wherein said latching means comprises two latching portions each for storing n bits, said two latching portions alternatively latching input signals in response to a clock signal having a frequency of f 0 /2n, said apparatus further comprising selecting means for selecting the outputs of said latching means to output (2n-1) bits of information to said parallel synchronization detecting means.

Claim 20

A frame synchronizing apparatus as set forth in claim 12, further comprising a timing signal generating circuit having an output counter with n kinds of phases, for providing a timing signal to said latching means, one of said phases being selected in response to the output of the detecting portion in said parallel synchronization detecting means that has detected the synchronization, whereby said latching means latches said parallel signals at the timing of said selected phases.

Claim 21

A frame synchronizing apparatus as set forth in claim 12, further comprising a timing signal generating circuit having a counter (3) for providing a timing signal to said latching means, said parallel synchronization detecting means comprising a synchronization control portion (13a) and a shift pulse generating portion (16) controlled by said synchronization control portion (13a), said timing signal being supplied to said latching means by shifting the count value of said counter in response to the pulse from said shift pulse generating portion (16).

Claim 22

A frame synchronizing apparatus as set forth in claim 17, wherein said latching means comprises two latching portions (2A, 2B) alternatively latching input signals in response to a clock signal having a frequency of fo/2n, said apparatus further comprising selecting means (2C) for selecting the outputs of said latching means to output (2n-1) bits of information to said parallel synchronization detecting means.