Patent US2435332A successfully refreshed from Google Patents.
US4802192A
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Circuit for detecting synchronizing code
Assignee: Hitachi Ltd
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Filing: 1987-02-10
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Granted: 1989-01-31
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Expires: 2007-02-10
Abstract
Abstract An original code series containing a synchronizing code is divided into code series, n in number so as to reduce an operation rate to 1/n (n is a positive integer). The detection of a synchronizing pattern is conducted on the basis of a fact that an original synchronizing pattern is transformed into any of patterns of n kinds based on the phase of division.
Inventors
- 👤 Yoshizumi Eto
- 👤 Kazuyuki Takeshita
- 👤 Hidehiro Kanada
- 👤 Masuo Umemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:16
CPC Classifications
G; G11; G11B; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
152 words
A synchronizing code detection circuit comprising: dividing means for dividing an original code series containing a synchronizing code into a code series, n in number, having a bit rate of 1/n of that of the original code series (n is a positive integer); delay means for delaying a code series, (n-m) in number, (m is a positive integer ranging from 1 to n) out of the code series, n in number, delivered from said dividing means, for a time equivalent to one time-slot of said bit rate of 1/n, respectively; and synchronizing pattern detecting means for detecting a pattern corresponding to any one of synchronizing patterns of n kinds obtained by rotating an original synchronizing pattern, from code series groups in n kinds comprising code series, m in number, out of the ones, n in number, delivered from said dividing means and code series, (n-m) in number, delivered from said delay means.
Claim 2
Dependent Claim
152 words
A synchronizing code detection circuit comprising: dividing means for dividing an original code series containing a synchronizing code into a code series, n in number, having a bit rate of 1/n of that of the original code series (n is a positive integer); delay means for delaying a code series, (n-m) in number, (m is a positive integer ranging from 1 to n) out of the code series, n in number, delivered from said dividing means, for a time equivalent to one time-slot of said bit rate of 1/n, respectively; and synchronizing pattern detecting means for detecting a pattern corresponding to any one of synchronizing patterns of n kinds obtained by rotating an original synchronizing pattern, from code series groups in n kinds comprising code series, m in number, out of the ones, n in number, delivered from said dividing means and code series, (n-m) in number, delivered from said delay means.
Claim 3
Dependent Claim
177 words
A synchronizing code detection circuit comprising: a serial-parallel converter which divides an original code series containing a synchronizing code into a code series, n in number (n is a positive integer) having a bit rate of 1/n of that of the original code series; a plurality of delay devices which delay a code series, (n-m) in number, (m is a positive integer ranging from 1 to n) out of the code series, n in number, delivered from said serial-parallel converter, respectively, for a time equivalent to one time-slot of said bit rate of 1/n; a plurality of synchronizing pattern detection circuits which detect a pattern corresponding to any one of synchronizing patterns of n kinds obtained by rotating an original synchronizing pattern, respectively, from code series groups on n kinds comprising code series, m in number, out of the ones, n in number, delivered from said serial-parallel converter and code series, (n-m) in number, delivered from said delay devices respectively; and an output circuit which delivers an output of any one of said synchronizing pattern detection circuits.
Claim 4
Dependent Claim
177 words
A synchronizing code detection circuit comprising: a serial-parallel converter which divides an original code series containing a synchronizing code into a code series, n in number (n is a positive integer) having a bit rate of 1/n of that of the original code series; a plurality of delay devices which delay a code series, (n-m) in number, (m is a positive integer ranging from 1 to n) out of the code series, n in number, delivered from said serial-parallel converter, respectively, for a time equivalent to one time-slot of said bit rate of 1/n; a plurality of synchronizing pattern detection circuits which detect a pattern corresponding to any one of synchronizing patterns of n kinds obtained by rotating an original synchronizing pattern, respectively, from code series groups on n kinds comprising code series, m in number, out of the ones, n in number, delivered from said serial-parallel converter and code series, (n-m) in number, delivered from said delay devices respectively; and an output circuit which delivers an output of any one of said synchronizing pattern detection circuits.
Claim 5
Dependent Claim
178 words
A synchronizing code detection circuit comprising: a serial-parallel converter which divides an original code series containing a synchronizing code into a code series, n in number, (n is a positive integer) having a bit rate of 1/n of that of the original code series; a plurality of delay devices which delay a code series, (n-m) in number, (m is a positive integer ranging from 1 to n) out of the code series, n in number, delivered from said serial-parallel converter, respectively, for a time equivalent to one time-slot of said bit rate of 1/n; a plurality of synchronizing pattern detection circuits which detect a pattern corresponding to any one of synchronizing patterns of n kinds obtained by rotating an original synchronizing pattern, respectively, from code series groups of n kinds comprising code series, m in number, out of the ones, n in number, delivered from said serial-parallel converter and code series, (n-m) in number, delivered from said delay devices respectively; and a logical sum circuit which delivers an output of any one of said synchronizing pattern detection circuits.
Claim 6
Dependent Claim
178 words
A synchronizing code detection circuit comprising: a serial-parallel converter which divides an original code series containing a synchronizing code into a code series, n in number, (n is a positive integer) having a bit rate of 1/n of that of the original code series; a plurality of delay devices which delay a code series, (n-m) in number, (m is a positive integer ranging from 1 to n) out of the code series, n in number, delivered from said serial-parallel converter, respectively, for a time equivalent to one time-slot of said bit rate of 1/n; a plurality of synchronizing pattern detection circuits which detect a pattern corresponding to any one of synchronizing patterns of n kinds obtained by rotating an original synchronizing pattern, respectively, from code series groups of n kinds comprising code series, m in number, out of the ones, n in number, delivered from said serial-parallel converter and code series, (n-m) in number, delivered from said delay devices respectively; and a logical sum circuit which delivers an output of any one of said synchronizing pattern detection circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-31 | 1992-08-01 | 1993-01-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-31 | 1996-08-01 | 1997-01-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-31 | 2000-08-01 | 2001-01-31 | $7700.00 | Window Closed / Lapsed |