Patent US4920400A successfully refreshed from Google Patents.
US4920400A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Japan Science and Technology Agency
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Filing: 1989-01-18
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Granted: 1990-04-24
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Expires: 2009-01-18
Abstract
Abstract A semiconductor device comprising a pair of p-type regions facing each other, a pair of n-type regions facing each other, and a nearly intrinsic region connecting these regions, thereby establishing a hole current path connecting the p-type regions and an electron current path connecting the n-type regions. Each of the hole current path and the electron current path has a transfer function which is a function of structural parameters of the device and the applied biases. The electron current path and the hole current path can provide a complementary pair of outputs.
Inventors
- 👤 Istyan Barsony
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 22:10
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/202; H10D84/00; H10D84/80; H10D84/87
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
170 words
A semiconductor device having a main body region of a substantially intrinsic semiconductor two pairs of terminals defined by electrode regions, one of said pairs being of a p-type conductivity and the other pair being of an n-type, the built-in potentials of said terminals inducing a single potential barrier in said main body, whereby two controlled current paths are formed, each passing through said potential barrier and between a different one of said pairs of terminals, so that said two current paths comprise one electron path for allowing flow of a majority current formed of electrons and one hole path for allowing flow of a majority current formed of holes, the two paths being non-interacting, each current path having a current flow defined by a predetermined transfer function representing the relationship between current in the respective path and the height of said single potential barrier structure, said device being constructed so that said potential barrier height is controlled by input voltages applied to said pairs of terminals of the device.
Claim 2
Dependent Claim
170 words
A semiconductor device having a main body region of a substantially intrinsic semiconductor two pairs of terminals defined by electrode regions, one of said pairs being of a p-type conductivity and the other pair being of an n-type, the built-in potentials of said terminals inducing a single potential barrier in said main body, whereby two controlled current paths are formed, each passing through said potential barrier and between a different one of said pairs of terminals, so that said two current paths comprise one electron path for allowing flow of a majority current formed of electrons and one hole path for allowing flow of a majority current formed of holes, the two paths being non-interacting, each current path having a current flow defined by a predetermined transfer function representing the relationship between current in the respective path and the height of said single potential barrier structure, said device being constructed so that said potential barrier height is controlled by input voltages applied to said pairs of terminals of the device.
Claim 3
Dependent Claim
24 words
A semiconductor device according to claim 1, wherein said two current paths are substantially orthogonal within a region of said device including said barrier.
Claim 4
Dependent Claim
23 words
A semiconductor device according to claim 1, wherein said device includes structural means for correlating the two transfer functions by a single function.
Claim 5
Dependent Claim
18 words
A semiconductor device according to claim 1, wherein said current paths occupy a three dimensional current distribution space.
Claim 6
Dependent Claim
38 words
A semiconductor device according to claim 1, wherein each of the current paths includes means for establishing a drift field, the drift fields of the two current paths being substantially orthogonal in the vicinity of the potential barrier.
References Cited (Backward Citations)
US3840888A
Cited
US4182965A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |