Semiconductor device having two intersecting sub-diodes and transistor-like properties

Claim 2

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and said connecting line between said second doped zones intersecting said connecting line between said first doped zones at right angles.

Claim 3

The device of claim 1 wherein the first external circuit means forward biases the first PIN diode and the second external circuit means reverse biases the second PIN diode such that holes and electrons respectively injected by the first P and N doped zones are respectively partially attracted by the second P and N doped zones.

Claim 4

A semiconductor device of claim 1 in which the substantially intrinsic base zone is weakly doped.

Claim 5

A semiconductor device of claim 1 in which the substrate is an insulator.

Claim 6

A semiconductor device of claim 1 in which the substrate is weakly conductive.

Claim 7

A semiconductor device as claimed in claim 1, characterized in that the semiconductor layer comprises silicon and the substrate is an insulator comprising sapphire.

Claim 8

A semiconductor device as claimed in claim 1, characterized in that the distance between the first P doped zone and the first N doped zone, and the distance between the second P doped zone and the second N doped zone is substantially greater than an average diffusion length of free charge carriers in the base zone.

Claim 9

A semiconductor device as claimed in claim 1, characterized in that at least one further pair comprised of a P doped zone and a N doped zone is provided, the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and the first N doped zone.

Claim 10

A semiconductor device as claimed in claim 1, characterized in that means are provided through which a magnetic field parallel to the surface of the semiconductor layer can be produced in the semiconductor device.

Claim 11

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and the distance between the first P doped zone and the first N doped zone, and the distance between the second P doped zone and the second N doped zone being shorter than or equal to the average diffusion length of free charge carriers in the base zone located between these doped zones.

Claim 12

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and the distance between the first P doped zone and the first N doped zone, and the distance between the second P doped zone and the second N doped zone being shorter than or equal to the average diffusion length of free charge carriers in the base zone located between these doped zones.

Claim 13

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and the distance between the second P doped zone and the second N doped zone being shorter than an average diffusion length of free charge carriers in the base zone, and the distance between the first P doped zone and the first N doped zone being considerably greater than said average diffusion length.

Claim 14

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and the distance between the second P doped zone and the second N doped zone being shorter than an average diffusion length of free charge carriers in the base zone, and the distance between the first P doped zone and the first N doped zone being considerably greater than said average diffusion length.

Claim 15

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; at least one further pair comprised of a P doped zone and a N doped zone being provided, the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and the first N doped zone; and the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and first N doped zone at right angles thereto.

Claim 16

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; at least one further pair comprised of a P doped zone and a N doped zone being provided, the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and the first N doped zone; and the connection lines between the P and N doped zones of each pair intersecting the connection line between the first P doped zone and first N doped zone at right angles thereto.

Claim 17

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and an insulating layer being provided on said semiconductor layer, and on said insulating layer there being arranged a field effect electrode which extends over the base zone.

Claim 18

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductor layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and an insulating layer being provided on said semiconductor layer, and on said insulating layer there being arranged a field effect electrode which extends over the base zone.

Claim 19

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductory layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and an input control signal source means being provided in the first external circuit means and an output load means being connected in the second external circuit means for creating an output signal which is an amplification of an input signal of the input control signal source means.

Claim 20

A semiconductor device comprising in combination: a substrate; a substantially intrinsic (I) semiconductor layer on the substrate; a first P doped zone and a first N doped zone in the semiconductor layer and separated by a portion of said semiconductory layer which serves as a base zone so as to form a first PIN diode; a second P doped zone and a second N doped zone in the semiconductor layer and separated by at least the portion of said semiconductor layer between the first P and first N doped zones so as to form a second PIN diode and such that a first charge carrier path between the first P and N doped zones crosses through a second charge carrier path between the second P and N doped zones, the first charge carrier path being positioned to influence the second charge carrier path; the first PIN diode being biased by a first external circuit means and the second PIN diode being biased by a second external circuit means, the first and second circuit means being independent of each other in such a fashion that all four zones may have different potentials; and an input control signal source means being provided in the first external circuit means and an output load means being connected in the second external circuit means for creating an output signal which is an amplification of an input signal of the input control signal source means.