US3710206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Negative impedance semiconductor device with multiple stable regions
Assignee: Sony Corp
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Filing: 1970-10-01
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Granted: 1973-01-09
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Expires: 1990-10-01
Abstract
Abstract An electrical circuit utilizing a semiconductor device to provide a novel negative impedance characteristic. The semiconductor device has, for example, four independent high impurity concentration regions formed on a semiconductor substrate, two of which regions inject carriers of opposite polarities into said substrate and another two of which regions are applied voltages so that junctions formed between said substrate and themselves are reversely biased to establish the desired negative impedance characteristics.
Inventors
- 👤 T Matsushita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:52
CPC Classifications
H; H10; H10D; H10D99/00; H10D10/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
153 words
A negative impedance circuit comprising: a semiconductor device having a substrate; first, second, third and fourth impurity concentration regions, each forming a separate junction with said substrate, said first and second regions being of opposite conductivity type to inject carriers of opposite polarity into said substrate and being spaced from each other by a distance greater than the diffusion distances of said carriers; means biasing said first and second regions to cause them to inject carriers of opposite polarity into said substrate to form a main current path between said first and second regions, said third and fourth regions being disposed on opposite sides of a substantially main part of said current path; and means for reversely biasing the junctions formed between said substrate and said third and fourth regions to produce a negative impedance effect between said first and second regions, wherein said third and fourth regions are of opposite conductivity type.
Claim 2
Dependent Claim
153 words
A negative impedance circuit comprising: a semiconductor device having a substrate; first, second, third and fourth impurity concentration regions, each forming a separate junction with said substrate, said first and second regions being of opposite conductivity type to inject carriers of opposite polarity into said substrate and being spaced from each other by a distance greater than the diffusion distances of said carriers; means biasing said first and second regions to cause them to inject carriers of opposite polarity into said substrate to form a main current path between said first and second regions, said third and fourth regions being disposed on opposite sides of a substantially main part of said current path; and means for reversely biasing the junctions formed between said substrate and said third and fourth regions to produce a negative impedance effect between said first and second regions, wherein said third and fourth regions are of opposite conductivity type.
Claim 3
Dependent Claim
206 words
A negative impedance circuit comprising: a semiconductor device having a substrate; first, second, third and fourth impurity concentration regions, each forming a separate junction with said substrate, said first and second regions being of opposite conductivity type to inject carriers of opposite polarity into said substrate and being spaced from each other by a distance greater than the diffusion distances of said carriers; means biasing said first and second regions to cause them to inject carriers of opposite polarity into said substrate to form a main current path between said first and second regions, said third and fourth regions being disposed on opposite sides of a substantially main part of said current path; and means for reversely biasing the junctions formed between said substrate and said third and fourth regions to produce a negative impedance effect between said first and second regions, wherein said substrate is pi -type and said first and second regions are respectively P- and N-types, and wherein said third and fourth regions are P-type and N-type respectively and said reversely biasing means includes a voltage source connected between said second and third regions which applies a negative voltage to the third region and a connection point between said first and fourth regions.
Claim 4
Dependent Claim
206 words
A negative impedance circuit comprising: a semiconductor device having a substrate; first, second, third and fourth impurity concentration regions, each forming a separate junction with said substrate, said first and second regions being of opposite conductivity type to inject carriers of opposite polarity into said substrate and being spaced from each other by a distance greater than the diffusion distances of said carriers; means biasing said first and second regions to cause them to inject carriers of opposite polarity into said substrate to form a main current path between said first and second regions, said third and fourth regions being disposed on opposite sides of a substantially main part of said current path; and means for reversely biasing the junctions formed between said substrate and said third and fourth regions to produce a negative impedance effect between said first and second regions, wherein said substrate is pi -type and said first and second regions are respectively P- and N-types, and wherein said third and fourth regions are P-type and N-type respectively and said reversely biasing means includes a voltage source connected between said second and third regions which applies a negative voltage to the third region and a connection point between said first and fourth regions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-09 | 1976-07-10 | 1977-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-09 | 1980-07-10 | 1981-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-09 | 1984-07-10 | 1985-01-09 | $7700.00 | Window Closed / Lapsed |