US4920064A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing an insulated gate field effect transistor DMOS
Assignee: US Philips Corp
•
Filing: 1989-04-18
•
Granted: 1990-04-24
•
Expires: 2009-04-18
Abstract
Abstract A method of manufacturing an insulated gate field effect transistor is described. The method comprises providing a gate layer (6) on an insulating layer (12) on one surface (4) of a semiconductor body (1) and source regions (2) of one conductivity type within a respective body region (14), a portion of each body region (14) underlying a portion of the gate layer to provide a channel area extending between the source region (2) and a drain region (3) meeting another surface (5) of the semiconductor body opposite the one surface (4). Each source region (2) is shorted to the corresponding body region (14) by opening a contact window (15) in the insulating layer on the one surface so as to expose a surface of the source region (2), providing resist masking regions (16) extending completely across the contact window in one direction so as to define an exposed area of the source region which is not covered by either the masking regions or the insulating layer ( 12), and has a periphery defined partly by the contact window and partly by the masking region(s), etching away the exposed area of the source region (2) to expose an underlying area of the body region (14), removing the masking regions and providing metallization within the contact window (15) to short the exposed area of the body region to the source region.
Inventors
- 👤 Kenneth R. Whight
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/60; H10D30/64; H10D30/66; H10D62/00; H10D62/10; H10D62/124; H10D62/126; H10D62/127; H10D64/00; H10D64/20; H10D64/23; H10D64/251; H10D64/252; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/519; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D64/2527; H10D64/256; Y; Y10; Y10S; Y10S148/00; Y10S148/106; Y10S148/126
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
291 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of providing an insulating layer on one surface of a semiconductor body, said semiconductor body being of a first conductivity type; providing a conductive gate layer on at least portions of said insulating layer to form an insulated gate structure having at least one conductive gate region; introducing impurities into said semiconductor body through said insulating layer in areas adjacent said insulative gate structure to form at least one source region at said one surface within at least one body region of said semiconductor body, said source region being of a second conductivity type opposite to said first conductivity type; forming at least one channel region below said gate region; covering said insulated gate structure with another insulating layer by growing insulating material on said one surface of said semiconductor body; opening at least one contact window in said another insulating layer to said one surface to expose a surface of said source region, providing a resist layer on said another insulating layer, and patterning said resist layer to form a plurality of masking regions on said one surface over at least a portion of said source region, said masking regions extending completely across said contact window in a first direction, and said masking regions only partly covering said contact window in a second direction, said source region having at least one exposed portion defined partially by said contact window and partially by said masking regions; etching away said exposed portion of said source region to expose underlying portions of said body region; removing said masking regions; and providing metallisation within said contact window to short said exposed underlying portions of said body region to said source region.
Claim 2
Independent Claim
291 words
A method of manufacturing an insulated gate field effect transistor comprising the steps of providing an insulating layer on one surface of a semiconductor body, said semiconductor body being of a first conductivity type; providing a conductive gate layer on at least portions of said insulating layer to form an insulated gate structure having at least one conductive gate region; introducing impurities into said semiconductor body through said insulating layer in areas adjacent said insulative gate structure to form at least one source region at said one surface within at least one body region of said semiconductor body, said source region being of a second conductivity type opposite to said first conductivity type; forming at least one channel region below said gate region; covering said insulated gate structure with another insulating layer by growing insulating material on said one surface of said semiconductor body; opening at least one contact window in said another insulating layer to said one surface to expose a surface of said source region, providing a resist layer on said another insulating layer, and patterning said resist layer to form a plurality of masking regions on said one surface over at least a portion of said source region, said masking regions extending completely across said contact window in a first direction, and said masking regions only partly covering said contact window in a second direction, said source region having at least one exposed portion defined partially by said contact window and partially by said masking regions; etching away said exposed portion of said source region to expose underlying portions of said body region; removing said masking regions; and providing metallisation within said contact window to short said exposed underlying portions of said body region to said source region.
Claim 3
Dependent Claim
49 words
A method according to claim 1, wherein said step of opening said contact window is carried out by anisotropically etching said another insulating layer toward said one surface of said semiconductor body, said another insulating layer remaining at edges of said insulated gate structure to define said contact window.
Claim 4
Dependent Claim
85 words
A method according to claim 1 or claim 2, wherein said masking region are provided by forming a plurality of masking areas completely across said contact window in said first direction, said plurality of masking areas being separated in said second direction to form a plurality of said exposed portions of said source region, and wherein each of said plurality of said exposed portions has a periphery defined partly by said contact window and partly by one or more of said plurality of masking areas.
Claim 5
Dependent Claim
69 words
A method according to claim 3, wherein said step of opening said contact window is carried out by opening an elongated contact window extending in said second direction, said plurality of masking areas extending completely across a width of said elongated contact window in said first direction, and said plurality of masking areas extending only across portions of a length of said elongated contact window in said second direction.
Claim 6
Dependent Claim
60 words
A method according to claim 4, wherein said plurality of masking areas are formed substantially mutually parallel across said elongated contact window in said first direction, wherein said plurality of masking areas are formed spaced apart in said second direction, and wherein a number of spaced apart exposed portions of said source region are provided within said elongated contact window.
Claim 7
Dependent Claim
21 words
A method according to claim 5, wherein said plurality of masking areas are formed equally spaced apart in said second direction.
Claim 8
Dependent Claim
43 words
A method according to claim 5, wherein said number of spaced apart exposed portions of said source region are formed with a first area, said first area being equal to a second area of said plurality of masking areas covering said source region.
Claim 9
Dependent Claim
41 words
A method according to claim 4, wherein said plurality of masking areas are formed by apertures in said masking region, and wherein each of said apertures is formed with a width dimension larger than said width of said elongated contact window.
Claim 10
Dependent Claim
47 words
A method according to claim 4, further comprising, between said steps of etching away and removing, the further step of introducing further impurities of said first conductivity type through said contact window, said further impurities increasing surface doping of the exposed underlying portions of said body region.
Claim 11
Dependent Claim
85 words
A method according to claim 4, wherein said step of introducing impurities is carried out at opposite sides of said gate regions to form respective source regions in associated body regions at each of said opposite sides, said associated body regions forming respective ones of said channel regions under said opposite sides of said gate region, and wherein each of said respective source regions is shorted to said associated body region, respective ones of said contact windows being opened over each of said source regions.
Claim 12
Independent Claim
71 words
A method according to claims 1 or 2, wherein said step of opening said contact window is carried out by opening an elongated contact window extending in said second direction, wherein a plurality of masking areas extend completely across a width of said elongated contact window in said first direction, said plurality of masking areas extending only across portions of a length of said elongated contact window in said second direction.
Claim 13
Dependent Claim
60 words
A method according to claim 11, wherein said plurality of masking areas are formed substantially mutually parallel across said elongated contact window in said first direction, wherein said plurality of masking areas are formed spaced apart in said second direction, and wherein a number of spaced apart exposed portions of said source region are provided within said elongated contact window.
Claim 14
Dependent Claim
21 words
A method according to claim 12, wherein said plurality of masking areas are formed equally spaced apart in said second direction.
Claim 15
Dependent Claim
43 words
A method according to claim 12, wherein said number of spaced apart exposed portions of said source region are formed with a first area, said first area being equal to a second area of said plurality of masking areas covering said source region.
Claim 16
Dependent Claim
41 words
A method according to claim 11, wherein said plurality of masking areas are formed by apertures in said masking region, and wherein each of said apertures is formed with a width dimension larger than said width of said elongated contact window.
Claim 17
Dependent Claim
49 words
A method according to claim 1 or 2, further comprising, between said steps of etching away and removing, the further step of introducing further impurities of said first conductivity type through said contact window, said further impurities increasing surface doping of the exposed underlying portions of said body region.
Claim 18
Dependent Claim
87 words
A method according to claim 1 or 2, wherein said step of introducing impurities is carried out at opposite sides of said gate regions to form respective source regions in associated body regions at each of said opposite sides, said associated body regions forming respective ones of said channel regions under said opposite sides of said gate region, and wherein each of said respective source regions is shorted to said associated body region, respective ones of said contact windows being opened over each of said source regions.
References Cited (Backward Citations)
US4021270A
Cited
US4182636A
Cited
EP0038994A2
Cited
EP0067475A2
Cited
US4598461A
Cited
US4567641A
Cited
US4503598A
Cited
US4466176A
Cited
DE3402867A1
Cited
US4692998A
Cited
US4648174A
Cited
US4632724A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-23 | 1993-10-23 | 1994-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-23 | 1997-10-23 | 1998-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-23 | 2001-10-23 | 2002-04-24 | $7700.00 | Window Closed / Lapsed |