Patent US4918403A successfully refreshed from Google Patents.
US4918403A
Expired / Lapsed
US
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Frequency synthesizer with spur compensation
Assignee: Quarterhill Inc
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Filing: 1989-03-27
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Granted: 1990-04-17
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Expires: 2009-03-27
Abstract
Abstract A synthesizer circuit with spur compensation utilizes fractional division in the synthesizer loop. Two accumulators are utilized for determining the divisor value N. The capacity of the two accumulators is selectable. An offset value is selectively introduced into the accumulators in order to produce a waveform having an acceptable spurious content.
Inventors
- 👤 Frederick L. Martin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 09:15
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/197; H03L7/1974; H03L7/1976
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
145 words
A frequency synthesizer for providing a synthesized output frequency f o comprising: a synthesizer loop including a programmable divider; memory means for providing information for said synthesizer loop; a divider control means providing divider values to said programmable divider, said divider control means providing varying values to said programmable divider for fractional division to produce a desired output frequency f o , and including at least a first and second accumulator means; said first accumulator means including an input for receiving data, a first output for varying said divide value, and a second output for providing data to said second accumulator means, and said second accumulator means including an input connected to said second output of said first accumulator means and an output for varying said divide value; means for providing an offset value to at least one of said first and second accumulator means.
Claim 2
Dependent Claim
145 words
A frequency synthesizer for providing a synthesized output frequency f o comprising: a synthesizer loop including a programmable divider; memory means for providing information for said synthesizer loop; a divider control means providing divider values to said programmable divider, said divider control means providing varying values to said programmable divider for fractional division to produce a desired output frequency f o , and including at least a first and second accumulator means; said first accumulator means including an input for receiving data, a first output for varying said divide value, and a second output for providing data to said second accumulator means, and said second accumulator means including an input connected to said second output of said first accumulator means and an output for varying said divide value; means for providing an offset value to at least one of said first and second accumulator means.
Claim 3
Dependent Claim
106 words
The frequency synthesizer of claim 1 wherein said means for providing said offset value comprises: a data register means, said data register means including an input from said memory means to provide said data and said offset value, a first output for providing said data and a second output for providing said offset value for each desired output frequency f o ; an offset control means for selecting said second output of said data register means; and a multiplexer coupled to said first and second outputs of said data register means for providing said offset value to said accumulator in response to said offset control means.
Claim 4
Dependent Claim
25 words
The frequency synthesizer of claim 2 wherein said offset control means comprises inverting and delaying means coupled to a series of at least three flip-flops.
Claim 5
Dependent Claim
92 words
The frequency synthesizer of claim 3 wherein said offset control means comprises: a series circuit including at least a first and a second inverter and a delay element, said output of said series circuit is connected to a clock input of said third flip-flop; said second flip-flop includes a clock input for coupling to an output of said first inverter; and a NOR gate including inputs connected to a Q bar output of said second and of said third flip-flop and an output coupled to a reset input of said first flip-flop.
Claim 6
Independent Claim
89 words
A method of providing a synthesized output frequency, comprising the steps of: (a) receiving data for providing a divider value to a programmable divider; (b) offsetting said data to provide an offset data; (c) accumulating said offset data to provide an accumulated signal and a first control signal; (d) accumulating said accumulated signal to provide a second control signal; (e) delaying and inverting said second control signal to provide a third control signal; and (f) varying said divider value in response to said first, second, and third control signals.
Claim 7
Independent Claim
89 words
A method of providing a synthesized output frequency, comprising the steps of: (a) receiving data for providing a divider value to a programmable divider; (b) offsetting said data to provide an offset data; (c) accumulating said offset data to provide an accumulated signal and a first control signal; (d) accumulating said accumulated signal to provide a second control signal; (e) delaying and inverting said second control signal to provide a third control signal; and (f) varying said divider value in response to said first, second, and third control signals.
Claim 8
Independent Claim
91 words
A method of providing a synthesized output frequency, comprising the steps of: (a) receiving data for providing a divider value to a programmable divider; (b) accumulating said data to provide an accumulated signal and a first control signal; (c) offsetting said accumulated signal to provide an offset accumulated signal; (d) accumulating said offset accumulated signal to provide a second control signal; (e) delaying and inverting said second control signal to provide a third control signal; and (f) varying said divider value in response to said first, second, and third control signals.
Claim 9
Independent Claim
91 words
A method of providing a synthesized output frequency, comprising the steps of: (a) receiving data for providing a divider value to a programmable divider; (b) accumulating said data to provide an accumulated signal and a first control signal; (c) offsetting said accumulated signal to provide an offset accumulated signal; (d) accumulating said offset accumulated signal to provide a second control signal; (e) delaying and inverting said second control signal to provide a third control signal; and (f) varying said divider value in response to said first, second, and third control signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-16 | 1993-10-16 | 1994-04-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-16 | 1997-10-16 | 1998-04-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-16 | 2001-10-16 | 2002-04-17 | $7700.00 | Window Closed / Lapsed |